How is the failure rate of that packaging any different to the failure rate of packaging a larger monolithic die anyway? You're introducing a constant that applies to both big monolithic and small MCM products alike; It's not relevant.
Not theoretical bullshit, caculated using one of many similar, industry-standard tools; More of the wafer on the right is white, orange or magenta. Less of it is green.
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Above is Zen2 8C/16T vs Renoir 8C/16T. AMD actually get more than twice as many Zen2 chiplets for the same money. Even ignoring the exponents, the sheer die area increase alone is enough to cause significant cost increases of the end product. AMD pay TSMC the same per wafer and the same to run that wafer through the fab no matter what product they etch into that wafer. Put yourself in AMD's shoes and ask yourself if you want to sell 780 products per wafer at $450 each or 322 products per wafer at $470 each? It's okay, I'll wait....