Discussed with some others and they seem to agree with me, but lets say I am wrong and for some reason its decided to require cpu connected pcie lanes. How could the DirectIO software determine if a nvme drive is connected that way? from what I can tell there is no distinction, its still connected via 4 lanes, and it runs at the same nvme specification with the same performance characteristics. So I think it may not even be possible to enforce even if they wanted to.
Also
Well yeah this is what I have been trying to tell you, you making assumptions based on theory, and the speedup in the new i/o stack is optimisations to the software stack as to how the data is read, the bottleneck is the sata protocol and i/o stack not the chipset interface. Plus that gpu hardware can handle the data decompression etc. faster than a typical cpu can.
Those nvme performance reviews are relevant to the point to prove that in a typical system the chipset link doesnt strangle a nvme drive. You would maybe have issues though if trying to read from multiple nvme drives at the same time over the chipset or have some other bandwidth heavy device running there, but these are very rare cases in consumer pc's.
We simply going to have to wait and see.
