AMD Embedded Roadmap Lists Zen 4 EPYC CPU with 64+ Cores

[Uskompuf]

The AMD embedded roadmap for 2020 - 2023 was recently leaked and reveals some interesting information about AMD's upcoming Zen 4 based EPYC server processes. The current generation 7003 series of Zen 3 EPYC processors offer up to 64 cores and 128 threads with a TDP range of 120 W - 280 W. The next-generation EPYC 7004 "Genoa" Zen 4 processors will push the maximum core count to 96 cores and 192 threads with a maximum TDP of 320 W. The Zen 4 based EPYC processors will move to a 12 chiplet design up from the current 8 chiplet design which allows for the core increase that will increase the physical size of the processors and require a new SP5 socket. The new EPYC 7004 series processors will also support the latest features such as 12 channel DDR5-5200 ECC memory and PCIe Gen5.



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[Final_Fighter]

So 48c 96t desktop processors will be possible.

 

[ZoneDymo]

It's all becoming a bit too much to comprehend, and not to be a downer but I'm already annoyed with with the undoubtedly upcoming ltt vid with linus (over)acting all shocked etc at the amount of threads showing up and then doing the exact same thing again with the epic after that till the end of time.

 

[theGryphon]

Yeah, I'm thinking it may be time for AMD to bifurcate: desktop focusing on architectural improvements to increase clocks.

 

[AnarchoPrimitiv]

Yeah, I'm thinking it may be time for AMD to bifurcate: desktop focusing on architectural improvements to increase clocks.

Clocks in and of themselves are meaningless, unless they're combined with high IPC
.. Intel should have taught you that lesson. Besides, TSMC has more control of the clock speeds than does AMD. I think everyone can agree that the clock speeds are irrelevant as long as the IPC is there, and with preliminary reports showing a 29% IPC uplift with Zen4 and 40% core for core performance increases, I don't think there's anything to complain about. Can anyone here cite when Intel did double digit IPC increases for three generations in a row?

 

[TumbleGeorge]

This is old from 2018 or 2019. In the past AMD team didn't know for that would be faster and bigger DDR5 modules, which was promised before few weeks.

 

[Dredi]

”The new EPYC 7004 series processors will also support the latest features such as 12 channel DDR5-5200 ECC memory and PCIe Gen5.”
@Uskompuf this is 99%+ false. The new processors will come with 24 channel DDR5 controllers. Otherwise the number of memory modules per socket would be less than before. Remember that DDR5 doubles the number of channels for the ~same pin count, and the channels are ~half as wide compared to DDR4.

Most leakers don’t understand how DDR5 works. Only 12 channels would be a joke and only barely faster than current 8 channel DDR4.

 

[Dammeron]

So 48c 96t desktop processors will be possible.

We already have those - Threadripper 3990 has 64 cores. However the price ain't too welcoming.

 

[TheinsanegamerN]

Yeah, I'm thinking it may be time for AMD to bifurcate: desktop focusing on architectural improvements to increase clocks.

Intel, a company far larger then AMD, uses the same arch across all but their atom lineup. How do you expect the much smaller AMD to manage this?

 

[theGryphon]

Clocks in and of themselves are meaningless, unless they're combined with high IPC
.. Intel should have taught you that lesson. Besides, TSMC has more control of the clock speeds than does AMD. I think everyone can agree that the clock speeds are irrelevant as long as the IPC is there, and with preliminary reports showing a 29% IPC uplift with Zen4 and 40% core for core performance increases, I don't think there's anything to complain about. Can anyone here cite when Intel did double digit IPC increases for three generations in a row?

Did I say IPC is not important? Instead of trying to teach me a lesson for what I didn't say, read exactly what I said.
I'm not 11 to learn the difference between IPC and clock speeds, thank you. At the current state, what AMD lacks in desktop is the clock speed advantage; they already have the IPC advantage. Hence my comment on what they should do to really reap those IPC gains against INTEL, who (like you said) is playing the clock speed card to close the IPC gap in the end products.

Intel, a company far larger then AMD, uses the same arch across all but their atom lineup. How do you expect the much smaller AMD to manage this?

I'm not saying a completely different arch; that would be absurd. Bifurcate, meaning, differentiate in a way to benefit them most in respective markets (desktop vs HPC). It's not going to see fruits immediately, so I bet AMD already has this mindset and working in the background. In essence, I wasn't giving AMD any groundbreaking idea. I was simply foretelling what's to come from them anyway, in the next 3-5 years

 

[1d10t]

8 core desktop would be mainstream someday.

 

[Wirko]

”The new EPYC 7004 series processors will also support the latest features such as 12 channel DDR5-5200 ECC memory and PCIe Gen5.”
@Uskompuf this is 99%+ false. The new processors will come with 24 channel DDR5 controllers. Otherwise the number of memory modules per socket would be less than before. Remember that DDR5 doubles the number of channels for the ~same pin count, and the channels are ~half as wide compared to DDR4.

Most leakers don’t understand how DDR5 works. Only 12 channels would be a joke and only barely faster than current 8 channel DDR4.

Expect a lot of confusion in the months that follow. Micron also mentions "sub-channels" in this and other documents, and that isn't helping to clear that confusion.

There's something else to consider here: it's not necessary to actually make use of the granularity that DDR5 offers (32 instead of 64 bits); it's optional. For example, the new Epyc's memory controller could be only able to control 12 channels independently, each of them being 64 bits wide. With a free gear-box on top of all that. It's perfectly possible that AMD (and not only them) have to resort to such tricks to keep the chip complexity and heat output half-reasonable.