AMD Shares New Details on Their 3D V-Cache Tech for Zen 3+

[mtcn77]

Jesus, that reduced distance for lowering the IMC latency is probably going to have a big performance gain on its own

And power, according to what they say on video.

 

[efikkan]

Something's bothering me: why did AMD use the prototype @ a fixed 4 GHz VS a regular 5900X also @ a fixed 4GHz, instead of the prototype @ "it's normal speed" VS the 5900X @ it's normal speed?

Yes, and it's a good example of why such estimates are fairly useless until we get proper independent tests.

Additionally, it's important to understand that gaming performance isn't a benchmark of CPU performance, despite the fact the CPU performance being important. The CPU only needs to be fast enough to not bottle neck the GPU, which is why we typically see diminishing returns with higher CPU speeds in gaming, first the FPS gains dry out, beyond that we gain better frame time consistency, until there are no more gains.
With current games, Skylake and Zen 3 already hit this point in most games around ~4.3-4.5 GHz. So even if this new CPU is significantly faster, it might not materialize as increased gaming performance, unless you underclock the CPUs as you mentioned.

Cache also improves IPC in multi threaded applications.

That depends on the instruction scheduler design, don't you think? Single block schedulers can access single ipc better, but multi ipc worse. I'm computer illiterate, sorry if I presented it wrong.

That is not all, hyperthreading and SMT changes instruction scheduler depth, a.k.a. ipc. The computer can do more, but with less single ipc. It looks like a stupid argument, but that is the general case with all excess testing.

Guys, you should refrain from using big words like IPC when you clearly don't understand what it means
IPC means instructions per clock, and is a measure of the average instructions per clock the architecture is capable of. IPC is not performance, but an underlying constant of the architecture which is independent of how many threads or cores which are involved, and is also workload independent. We usually use a single thread and a wide selection of workloads to approximate the relative IPC between different CPUs.
But whenever people mention "multithreaded IPC", "application specific IPC", SMT in relation to IPC, etc. that's a dead giveaway that they are clueless about what IPC really is. They are in fact talking about performance, not IPC.

From everything I've heard whatever was going to be Zen 3+ was cancelled, probably because of logistic issues caused by the pandemic, the lead they already have with Zen 3, and seeing just how well just the integration of this stacked cache turned out.

Do we have any actual evidence of the existence of "Zen 3+"?
Could it be that it was invented by the "leakers"?

 

[Dredi]

Guys, you should refrain from using big words like IPC when you clearly don't understand what it means
IPC means instructions per clock, and is a measure of the average instructions per clock the architecture is capable of. IPC is not performance, but an underlying constant of the architecture which is independent of how many threads or cores which are involved, and is also workload independent. We usually use a single thread and a wide selection of workloads to approximate the relative IPC between different CPUs.
But whenever people mention "multithreaded IPC", "application specific IPC", SMT in relation to IPC, etc. that's a dead giveaway that they are clueless about what IPC really is. They are in fact talking about performance, not IPC.

You are the clueless one. There are only application specific IPC, and theoretical IPC (which you can usually calculate from some datasheet by adding up all execution units in a core design, and completely useless for determining real world system level IPC). Everything else is just an opinion. Saying that IPC is a constant is a dead giveaway that the writer does not understand what the term means.

If IPC is some constant as you state, please give the IPC figure of any processsor currently in production, as a floating point number, and how that was measured.

edit: also, who the f is ”we” in your text?

you seem to be describing what relative single threaded performance at a fixed clock frequency is. That has very little to do with ”IPC”.

 

[TheoneandonlyMrK]

I must admit, I'm also wondering why only one of the CCDs was "covered" with the new cache, and not both. But the thing that worries me more is that the die is now facing downwards, and most of the excess silicon is removed before the cache is then placed on top of it - my worry is increased thermals, and maybe that's why is was running at a slower speed?

I hope it's not some kind of thermal compromise where the CPU will clock down when under high use.

It was running at the same exact speed as that cpu compared to it, to accurately present the IP gain during a world wide customer presentation, on purpose.
Leaving final speeds and performance relatively wide open on purpose, imagine Intel's engineering spec team now, I bet they're in work this weekend.
There's a cache per CCD AFAIK ?!
As for thermal worries, we've had them year's, they're not going away. ..

 

[rusTORK]

It was running at the same exact speed as that cpu compared to it, to accurately present the IP gain during a world wide customer presentation, on purpose.

I must admit, I'm also wondering why only one of the CCDs was "covered" with the new cache, and not both.

When i first time saw picture i got same question. Only after few days i got it - It's not two CPUs (original 5900X vs 5900X with 3D V-Cache), it's SAME CPU. They made prototype with equal CCDs when one CCD of them with 3D V-Cache. That's why it have got same frequency 4GHz. It's just easy to compare on one CPU. You simply may run benchmark on CCD1 and then run same benchmark on CCD2 with 3D V-Cache and see performance gain.

 

[stimpy88]

When i first time saw picture i got same question. Only after few days i got it - It's not two CPUs (original 5900X vs 5900X with 3D V-Cache), it's SAME CPU. They made prototype with equal CCDs when one CCD of them with 3D V-Cache. That's why it have got same frequency 4GHz. It's just easy to compare on one CPU. You simply may run benchmark on CCD1 and then run same benchmark on CCD2 with 3D V-Cache and see performance gain.

Interesting! So it was essentially 2 5800x's?

I would love to get my hands on that and see the impact of this cache. I'm interested in the impact on heat, voltage/current and clocks.

 

[Xajel]

Something's bothering me: why did AMD use the prototype @ a fixed 4 GHz VS a regular 5900X also @ a fixed 4GHz, instead of the prototype @ "it's normal speed" VS the 5900X @ it's normal speed?

Either they don't yet know what "it's normal speed" will end up being, which is actually quite likely, or this prototype will end up having a lower frequency than the 5900X due to it's new "3D nature", meaning that 15% improvement might not actually be as much as it seems to be.

Ofc, that 15% @ 4 GHz is only with the 3D V-cache without anything else, so it's still possible that the new Zen 3+ CPU could still end up being 15%+ faster than the 5900X WHILE having ... say ... 400 to 500 MHz LESS frequency, depending on WHAT ELSE is being changed VS Zen 3.

I guess because different chips behave differently. They wanted to omit any chip lottery even though they control every thing, but still not all silicons are equals. So they just went for a direct clock for clock comparison. And because they can turn on/off the extra V-Cache, they can also test the power different by retesting the same CPU again and again.

There's rumour about Zen3+ being a slightly new design compared to Zen3 with extra IPC improvements, but those rumours are conflicting as hell, some says they cancelled it, some says it hasn't been there to cancel it in the first place, and some says it's just the exact same Zen3 design with the V-Cache, that's why there are many conflicting rumours around which makes all these rumours plausible in the same time.

 

[Mussels]

I guess because different chips behave differently. They wanted to omit any chip lottery even though they control every thing, but still not all silicons are equals. So they just went for a direct clock for clock comparison. And because they can turn on/off the extra V-Cache, they can also test the power different by retesting the same CPU again and again.

There's rumour about Zen3+ being a slightly new design compared to Zen3 with extra IPC improvements, but those rumours are conflicting as hell, some says they cancelled it, some says it hasn't been there to cancel it in the first place, and some says it's just the exact same Zen3 design with the V-Cache, that's why there are many conflicting rumours around which makes all these rumours plausible in the same time.

well of course AMD would have tested *all* those options

If they found out zen3 works well for minimal cost but good gains just by adding the V-cache, they'd shuffle the new designs and ideas off for AM5 chips instead

 

[stimpy88]

...If they found out zen3 works well for minimal cost but good gains just by adding the V-cache, they'd shuffle the new designs and ideas off for AM5 chips instead

This also bothers me. This whole Zen3+ thing is confusing. I can finally buy a 5900x/5950x now, but am holding off because I simply cannot believe that AM4 is done. DDR5 is not ready, expensive, and slower than DDR4.

I really think AMD should release one last hurrah for AM4, to give DDR5 a chance to be available, and performant compared to DDR4. A double release towards the end of this year of the AM5 platform and one last CPU for AM4 would be perfect for the market. But who knows...

 

[Mussels]

This also bothers me. This whole Zen3+ thing is confusing. I can finally buy a 5900x/5950x now, but am holding off because I simply cannot believe that AM4 is done. DDR5 is not ready, expensive, and slower than DDR4.

I really think AMD should release one last hurrah for AM4, to give DDR5 a chance to be available, and performant compared to DDR4. A double release towards the end of this year of the AM5 platform and one last CPU for AM4 would be perfect for the market. But who knows...

with all the shortages, they have to continue AM4 for a bit

they simply wouldnt be able to get enough stock for sales of AM5 when it needs new CPUs, mobos and RAM, if they abandon AM4

So AM4 should get one last hurrah, a zen3+ to keep using the existing stock and keep sales up while preparing stock for AM5 as a lower quantity, high priced premium option for early adopters... if you know you're gunna sell less products, market them as premium and up the price


We also have those x570S chipset boards coming out, so we know the sockets not abandoned... why release new mobo chipsets and whole new series of boards from multiple vendors, if no new CPUs are coming?

 

[mtcn77]

This also bothers me. This whole Zen3+ thing is confusing. I can finally buy a 5900x/5950x now, but am holding off because I simply cannot believe that AM4 is done. DDR5 is not ready, expensive, and slower than DDR4.

Personally, I find it like the muscle car enthusiasm. Sure you can wait to see what comes out of the pipeline, but outside of minute distinctions, the tdp tiers are the same.

 

[Wirko]

with all the shortages, they have to continue AM4 for a bit

they simply wouldnt be able to get enough stock for sales of AM5 when it needs new CPUs, mobos and RAM, if they abandon AM4

So AM4 should get one last hurrah, a zen3+ to keep using the existing stock and keep sales up while preparing stock for AM5 as a lower quantity, high priced premium option for early adopters... if you know you're gunna sell less products, market them as premium and up the price


We also have those x570S chipset boards coming out, so we know the sockets not abandoned... why release new mobo chipsets and whole new series of boards from multiple vendors, if no new CPUs are coming?

I'm thinking along the same lines as you, mostly ... but what's the most probable timeline, from today's point of view?

So many details are floating around regarding AM5, I'd expect it to launch this year, but only for APUs (Rembrandt/Zen3+). Not as a premium option. APU users aren't the most demanding crowd, they can tolerate the initial quirks and non-optimum performance of the whole AM5 + DDR5 platform, including high RAM latencies, but graphics would benefit a lot from the DDR5 bandwidth. 3D V-cache? No, that costs a lot. Gears? Sure, like in everything else on DDR5.

Come to think of that, AM5 may even begin its life in an OEM-only launch.

The last and best round of AM4 chips could arrive at the same time, maybe even after first ones on AM5. 3D V-cache? Yes, and that costs a lot, so the CPUs will cost a lot too. About 20% or 25% more for 15% more performance, says the law of diminishing returns.

When i first time saw picture i got same question. Only after few days i got it - It's not two CPUs (original 5900X vs 5900X with 3D V-Cache), it's SAME CPU. They made prototype with equal CCDs when one CCD of them with 3D V-Cache. That's why it have got same frequency 4GHz. It's just easy to compare on one CPU. You simply may run benchmark on CCD1 and then run same benchmark on CCD2 with 3D V-Cache and see performance gain.

Well possibly - AMD can do all kinds of weird experiments, it's their chips. But don't take it for granted that it's possible to make an operative Ryzen CPU with asymmetrical configuration of cache. The one that Lisa showed could have been made just for her, that is, for showing off.
For testing without much hassle, AMD can build pairs of identical systems, with the only difference being the presence or absence of V-cache on both dies.

One of the most impressive bits of info was that the Zen 3 CCD was designed from the very beginning to be coupled with a stacked piece of cache. Anandtech reported that I think, and it really couldn't be another way, because you can't just put some extra static RAM on top of any random CPU and hope to connect it properly.

 

[Dwarden]

well, now try imagine they add 8GB HBM2E or HBM3 ontop of the I/O die for APU

it would sell like pancakes as no GPUs in sight