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It's happening, Intel is taking a very pointy stab at the AAA gaming graphics market, taking the fight to NVIDIA GeForce and AMD Radeon. The Arc "Alchemist" discrete GPU implements the Xe HPG (high performance gaming) graphics architecture, and offers full DirectX 12 Ultimate compatibility. It also offers contemporary features gamers want, such as XeSS, an AI-supersampling feature rivaling DLSS and FSR. There's a lot more to the Xe HPG architecture than being a simple a scale-up from the Xe LP-based iGPUs found in today's "Tiger Lake" processors.
Just like Compute Units on AMD GPUs, and Streaming Multiprocessors on NVIDIA, Intel designed a scalable hierarchical compute hardware structure for Xe HPG. It begins with the Xe-core, an indivisible compute building block that contains 16 each of 256-bit vector engines and 1024-bit matrix engines. combined with basic load/store hardware and an L1 cache. The vector unit here is interchangeable with the execution unit, and the Xe-core contains 16 of these. The Render Slice is a collective of four Xe-cores, four Raytracing Units; and other common fixed-function hardware that include the geometry pipeline, rasterization pipeline, samplers, and pixel-backends. The Raytracing Units contain fixed-function hardware for bounding-box intersection, ray traversal, and triangle intersection.
Moving a level up from the Render Slice, we see a Global Dispatch processor, and the GPU's memory fabric, which begins with an L2 cache. This is where Intel can scale up its GPUs. The 6 nm "Alchemist" silicon features eight Render Slices sharing the memory subsystem and Global Dispatch. Intel can carve out variants by toggling entire Render Slices, or perhaps even individual Xe-cores. With 16 EUs per Xe-core, 4 Xe-cores per Render Slice, and 8 Render Slices, we arrive at 512 execution units, or 4,096 programmable shaders.
Given that Xe HPG is being designed for the TSMC N6 (6 nm) silicon fabrication node, Intel claims a 50% performance/Watt gain over Xe LP solutions built on Intel's own 10 nm SuperFin nodes, such as the DG1 Iris Xe MAX. As a performance discrete GPU, "Alchemist" enjoys a much larger power budget, and hence operates at much higher frequencies for the available hardware.
Although not mentioned in the Intel presentation, it's been extensively reported that "Alchemist" (or DG2) features a 256-bit wide GDDR6 memory interface. The company is yet to determine memory size, but given the memory speeds available in the market (14 Gbps, 16 Gbps, and 18 Gbps), the memory bandwidth can end up anywhere between 448 GB/s to 576 GB/s.
Armed with as many as 512x 1024-bit Matrix cores backed by Xe Matrix extensions "Alchemist" is expected to be an AI processing powerhouse, with Intel leveraging them both for the XeSS performance enhancement feature, as well as other real-time rendering applications, such as de-noising for the raytracing pipeline.
Intel Arc "Alchemist" is expected to see a market release in Q1 2022. The company is ready with a roadmap with at least three of its successors, the Xe2 "Battlemage," Xe3 "Celestial," and XeNext "Druid." With no time-scale mentioned in the slide, we don't know if Intel is executing one architecture every year.
View at TechPowerUp Main Site
Just like Compute Units on AMD GPUs, and Streaming Multiprocessors on NVIDIA, Intel designed a scalable hierarchical compute hardware structure for Xe HPG. It begins with the Xe-core, an indivisible compute building block that contains 16 each of 256-bit vector engines and 1024-bit matrix engines. combined with basic load/store hardware and an L1 cache. The vector unit here is interchangeable with the execution unit, and the Xe-core contains 16 of these. The Render Slice is a collective of four Xe-cores, four Raytracing Units; and other common fixed-function hardware that include the geometry pipeline, rasterization pipeline, samplers, and pixel-backends. The Raytracing Units contain fixed-function hardware for bounding-box intersection, ray traversal, and triangle intersection.
Moving a level up from the Render Slice, we see a Global Dispatch processor, and the GPU's memory fabric, which begins with an L2 cache. This is where Intel can scale up its GPUs. The 6 nm "Alchemist" silicon features eight Render Slices sharing the memory subsystem and Global Dispatch. Intel can carve out variants by toggling entire Render Slices, or perhaps even individual Xe-cores. With 16 EUs per Xe-core, 4 Xe-cores per Render Slice, and 8 Render Slices, we arrive at 512 execution units, or 4,096 programmable shaders.
Given that Xe HPG is being designed for the TSMC N6 (6 nm) silicon fabrication node, Intel claims a 50% performance/Watt gain over Xe LP solutions built on Intel's own 10 nm SuperFin nodes, such as the DG1 Iris Xe MAX. As a performance discrete GPU, "Alchemist" enjoys a much larger power budget, and hence operates at much higher frequencies for the available hardware.
Although not mentioned in the Intel presentation, it's been extensively reported that "Alchemist" (or DG2) features a 256-bit wide GDDR6 memory interface. The company is yet to determine memory size, but given the memory speeds available in the market (14 Gbps, 16 Gbps, and 18 Gbps), the memory bandwidth can end up anywhere between 448 GB/s to 576 GB/s.
Armed with as many as 512x 1024-bit Matrix cores backed by Xe Matrix extensions "Alchemist" is expected to be an AI processing powerhouse, with Intel leveraging them both for the XeSS performance enhancement feature, as well as other real-time rendering applications, such as de-noising for the raytracing pipeline.
Intel Arc "Alchemist" is expected to see a market release in Q1 2022. The company is ready with a roadmap with at least three of its successors, the Xe2 "Battlemage," Xe3 "Celestial," and XeNext "Druid." With no time-scale mentioned in the slide, we don't know if Intel is executing one architecture every year.
View at TechPowerUp Main Site
