Intel Alder Lake-P Appears in Leaked Roadmap Featuring DDR5 & PCIe 5.0 Support

[Uskompuf]

Intel is expected to announce their desktop Alder Lake processors later this month on October 28th and it would appear that laptop processors could enter production as early as November. These revelations come from a leaked roadmap published by Wccftech that lists the Alder Lake-P and Alder Lake-M processor families for launch in Q4 2021 and Q1 2022 respectively. The production window for Alder Lake-P opens November 8th and closes March 13th while for Alder Lake-M that period is from January 17th to April 17th.

The roadmap lists Alder Lake-P processors as featuring a TDP between 12 W to 45 W and Alder Lake-M covering 7 W to 15 W. The two platforms will both feature up to 96 Xe graphics Execution units along with Thunderbolt 4 and WiFi 6E connectivity. Alder Lake-P will include PCIe 5.0 and DDR5 support with no mention of DDR4 compatibility while Alder Lake-M will get PCIe 4.0 and LPDDR4X/LPDDR5. The mobile lineup is divided into 3 groups of which the flagship H55 was not mentioned in the roadmap indicating a post Q1 2022 release.





The Alder Lake-M lineup will feature tablet and ultra-thin processors with core counts between 5 and 10 paired with 48 to 96 Xe Execution Units. The Alder Lake-P series will have products for mainstream, performance, and enthusiast devices with core counts ranging from 6 to 14 and 80 to 96 Xe Execution Units. The final H55 segment processors will feature 16 cores evenly split between high-efficiency and high-performance along with 32 Execution Units.

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[Crackong]

By 45W they mean 95W ?

 

[Metroid]

PCIe 4.0 first done by amd, now PCIe 5.0 first done by intel, competition is good cause now amd has to implement PCIe 5.0, faster nvme's I hope to utilize that speed.

 

[piloponth]

Ah, another week, another so called "leak" about AL.
Ya ya yah.

 

[Valantar]

PCIe 4.0 first done by amd, now PCIe 5.0 first done by intel, competition is good cause now amd has to implement PCIe 5.0, faster nvme's I hope to utilize that speed.

Given that current software and OSes are barely able to utilize PCIe 3.0-speed NVMe drives (and mostly not getting anywhere close to those speeds, even - look at the ATSB results, which are real-world application traces rather than synthetic benchmarks), that sounds rather utopian. The only real use case for PCIe 5.0 in the consumer space for the foreseeable future is lower lane count SSDs without sacrificing bandwidth, making controllers and motherboards easier (and hopefully a tiny bit cheaper) to make. Unless you have a very specialized workload, you're never going to make any noticeable use of the speed of a PCIe 5.0 SSD.

 

[Selaya]

wait i thought mobile cpus/socs are supposed to be power-efficient
no wonder crapple went with their own fucking m1s, intel's got all of this ass-backwards lmfao

 

[KarymidoN]

those leaks are almost becoming Press Releases for Intel...

 

[Valantar]

wait i thought mobile cpus/socs are supposed to be power-efficient
no wonder crapple went with their own fucking m1s, intel's got all of this ass-backwards lmfao

Is there any indicaiton of these not being power efficient?

 

[Selaya]

PCIe5?
(Which has like, no fucking place at all in mobile, PCIe 4 is already a stretch, since more bandwidth = more power, and that is simply not necessary for mobile?)

 

[Valantar]

PCIe5?
(Which has like, no fucking place at all in mobile, PCIe 4 is already a stretch, since more bandwidth = more power, and that is simply not necessary for mobile?)

That might be, but we don't really know yet. Intel's PCIe 4.0 implementation certainly doesn't seem to have harmed their efficiency meaningfully (which surprised me, at least).

 

[Selaya]

I mean, PCIe is reasonably smart in the sense that it automagically downgrades as long as the bandwidth is not necessary which means that, as long as your devices don't need that bandwidth they'll be in power-saving mode (also, probably basically no fucking one ever connecting anything PCIe 4 to their TGL laptops, but yeah).

But the question then is - if the feature is not supposed to be used, why implement it at all? Why waste precious silicon on it?

 

[Metroid]

Given that current software and OSes are barely able to utilize PCIe 3.0-speed NVMe drives (and mostly not getting anywhere close to those speeds, even - look at the ATSB results, which are real-world application traces rather than synthetic benchmarks), that sounds rather utopian. The only real use case for PCIe 5.0 in the consumer space for the foreseeable future is lower lane count SSDs without sacrificing bandwidth, making controllers and motherboards easier (and hopefully a tiny bit cheaper) to make. Unless you have a very specialized workload, you're never going to make awhich

Although at moment is just marketing and rivalry concerns, only specific cases will able able to utilize all the bandwidth pcie 5.0 offers.

 

[Valantar]

Although at moment is just marketing and rivalry concerns, only specific cases will able able to utilize all the bandwidth pcie 5.0 offers.

.... yes? That was what I said to you above. Are we in bizarro world suddenly? I was just saying that we don't know whether this will mean less power efficiency overall.

 

[mechtech]

When is ddr5 going to be available to mass market??

 

[Valantar]

When is ddr5 going to be available to mass market??

It'll likely start trickling out alongside the first platform to support it (which IIRC will be Alder Lake), but wide availability without a major price premium is likely a year or more out.

 

[repman244]

PCIe 4.0 first done by amd, now PCIe 5.0 first done by intel, competition is good cause now amd has to implement PCIe 5.0, faster nvme's I hope to utilize that speed.

The only sector which actually utilizes that speed and PCIe 4.0 is enterprise.