In August 2014, Intel announced that a bug exists in the TSX/TSX-NI implementation on Haswell, Haswell-E, Haswell-EP and early Broadwell CPUs, which resulted in disabling the TSX/TSX-NI feature on affected CPUs via a microcode update.
[9][10][23] The bug was fixed in F-0 steppings of the vPro-enabled Core M-5Y70 Broadwell CPU in November 2014.
[24]
The bug was found and then reported during a diploma thesis in the School of Electrical and Computer Engineering of the
National Technical University of Athens.
[25]
In October 2018, Intel disclosed a TSX/TSX-NI memory ordering issue found in
Skylake processors.
[26] As a result of a microcode update, HLE support was disabled in the affected CPUs, and RTM transactions would always abort in
SGX and
SMM modes of operation. System software would have to implement a workaround for the RTM memory ordering issue. In June 2021, Intel published a microcode update that further disables TSX/TSX-NI on various Xeon and Core processor models from
Skylake through
Coffee Lake and
Whiskey Lake as a mitigation for unreliable behavior of a performance counter in the Performance Monitoring Unit (PMU).
[27] By default, with the updated microcode, the processor would still indicate support for RTM but would always abort the transaction. System software is able to detect this mode of operation and mask support for TSX/TSX-NI from the
CPUID instruction, preventing detection of TSX/TSX-NI by applications. System software may also enable the "Unsupported Software Development Mode", where RTM is fully active, but in this case RTM usage may be subject to the issues described earlier, and therefore this mode should not be enabled on production systems.
According to Intel 64 and IA-32 Architectures Optimization Reference Manual from May 2020, Volume 1, Chapter 2.5 Intel Instruction Set Architecture And Features Removed,
[18] HLE has been removed from Intel products released in 2019 and later. RTM is not documented as removed. However, Intel 10th generation
Comet Lake and
Ice Lake CPUs, which were released in 2020, do not support TSX/TSX-NI,
[28][29][30][31][32] including both HLE and RTM.
In Intel Architecture Instruction Set Extensions Programming Reference revision 41 from October 2020,
[33] a new TSXLDTRK instruction set extension was documented and slated for inclusion in the upcoming
Sapphire Rapids processors.