AMD Details its 3D V-Cache Design at ISSCC

[TheLostSwede]

This week, the International Solid-State Circuits Conference is taking place online and during one of the sessions, AMD shared some more details of its 3D V-Cache design. The interesting part here is the overall design of AMD's 3D V-Cache, as well as how it interfaces with its CPU dies. The cache chip itself is said to measure 36 mm² and interfaces directly with the L3 cache using a Through Silicon Via or TSV interface. For all the CPU cores to be able to communicate with the 3D V-Cache, AMD has implemented a shared ring bus design at the L3 level. The entire L3 cache is said to be available to each of the cores, which should further help improve performance.

The 3D V-Cache is made up of multiple 8 MB "slices" which has a 1,024 contact interface with a single CPU core, for a total of 8,192 connections in total between the CCX and the 3D V-Cache. This allows for a bandwidth in excess of two terabyte per second, per slice, in full duplex mode. This should allow for full L3 speeds for the 3D V-Cache, despite the fact that it's not an integrated part of the CCX. AMD is also said to have improved the design of its CCX for the upcoming Ryzen 7 5800X3D in several ways to try and reduce the power draw, while improving clock speeds. AMD has yet to reveal a launch date for the Ryzen 7 5800X3D, but it'll be interesting to see if the 3D V-Cache and the various minor optimizations can make it competitive with Intel's Alder Lake CPUs until Zen 4 arrives.





Update: A few more slides from AMD's presentation have made their way online, which gives away some additional details. First and foremost, the SRAM used for the 3D V-Cache is manufactured by TSMC on the N7 node. AMD is referring to it as an "extended L3 Die" in the slides as well as a 64 MB L3 cache extension. The 3D V-Cache SRAM measures 41mm² and AMD has designed two additional structural supports of the CCD to help with thermal dissipation. To be able to fit everything into the same packaging as previous generation CPU's, AMD has had to thin the CCDs and L3 cache and the structural supports are also there to protect these thinned parts outside of the area covered by the 3D V-Cache.

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[jesdals]

Didnt AMD say that 3D V-cache wouldnt be a 7000 series thing? Shame it does sound interesting

 

[windwhirl]

Didnt AMD say that 3D V-cache wouldnt be a 7000 series thing? Shame it does sound interesting

It likely doesn't make sense to implement it in the entire 7000 series. I wouldn't be surprised if they hand-pick which model will have it.

At least for mainstream. Maybe on TR or EPYC it will be more commonly found.

 

[Deleted member 24505]

I guess it depends how costly it is to implement

 

[Xajel]

Didnt AMD say that 3D V-cache wouldnt be a 7000 series thing? Shame it does sound interesting

3D V-Cache is an advanced packaging technology, so it costs extra.

MCM costs less than 3D V-Cache yet AMD is finding it hard to make it for the budget Ryzen 3 CPUs, sure they did it before but now they're thinking of making Ryzen 3 only as APUs (a single monolithic die) to reduce the costs of packaging.

 

[Bruno Vieira]

Is this the First time AMD shows the dual ring between the cores? Ian (techtechpotato) has a video theorizing about it.

 

[ratirt]

3D V-Cache is an advanced packaging technology, so it costs extra.

MCM costs less than 3D V-Cache yet AMD is finding it hard to make it for the budget Ryzen 3 CPUs, sure they did it before but now they're thinking of making Ryzen 3 only as APUs (a single monolithic die) to reduce the costs of packaging.

monolithic die because the dies are way smaller (4 cores only) and everything can fit in there, also mitigating latency especially for the APU. Why divide it into 2 chiplets when one chiplet consists of 6-8 cores? Since when 3DVcache is packaging? It is stacking cache memory on top of each other to get more cache using way less space than traditional cache. It is not packaging solution. I'm having a problem seeing this not an MCM as a negative. Or maybe I understand you in a wrong way.

 

[TheLostSwede]

Is this the First time AMD shows the dual ring between the cores? Ian (techtechpotato) has a video theorizing about it.

Seems like it, yes. Not 100% sure.

 

[Tomorrow]

Also the updated 7nm B2 stepping adds more stable and higher boost clocks.

 

[TheLostSwede]

Also the updated 7nm B2 stepping adds more stable and higher boost clocks.

There's no proof of that though, it was just a rumour.

 

[Tomorrow]

There's no proof of that though, it was just a rumour.

Ok not higher boost but lower power and better temps. Also possibly better memory controller: https://www.guru3d.com/news-story/r...lower-consumption-and-lower-temperatures.html

According to overclocker Shamino's tests, these new CPUs have comparable overclocking capabilities to the Stepping B0, reaching 5.15GHz, but has 30W lower power consumption, allowing them to operate at a 9°C cooler temperature. Shamino also observed enhancements to the memory controller, allowing for the stable usage of 4100MHz memories, something that previously required numerous manual tweaks to work on CPUs with Stepping B0, indicating that these CPUs have several upgrades.

 

[TheLostSwede]

Ok not higher boost but lower power and better temps. Also possibly better memory controller: https://www.guru3d.com/news-story/r...lower-consumption-and-lower-temperatures.html

Still not enough sample size to be something that's widely confirmed.
This is not unusual though and we've seen this in plenty of chips in the past.

 

[mechtech]

64 megs is a huge cache, I wonder where diminishing returns occur?

From the 5700g vs 5800x some games were the same and some had good benefits from the 32meg vs 16 meg cache.

 

[DeathtoGnomes]

Still gotta wait for reviews to see performance. Wonder how soon to see an ES.

 

[Turmania]

So this cpu will be faster in clock speeds, consume less power and put out less heat than ryzen 7 5800X ? Is this what I'm suppose to understand.

 

[Deleted member 24505]

So this cpu will be faster in clock speeds, consume less power and put out less heat than ryzen 7 5800X ? Is this what I'm suppose to understand.

Should be faster, but use a tad more power for the extra cache

 

[SL2]

MCM costs less than 3D V-Cache yet AMD is finding it hard to make it for the budget Ryzen 3 CPUs, sure they did it before but now they're thinking of making Ryzen 3 only as APUs (a single monolithic die) to reduce the costs of packaging.

Here's an analogy for you, with cars of course.
Why go bashing in all the windows of your car and keying it before selling it, when you can sell it for more just as it is? Yeah, "you" being AMD here..

Using 8 core chiplets in 4 core CPU's isn't the reasonable thing to do. AMD will earn more money from that chiplet if it sits in a more expensive CPU.
Just imagine the price of a single chiplet, 4 core CPU, with a 8 chiplet, 64 core EPYC CPU. Hint: the latter cost more than eight times the price of the former. WAY more.

What did a Ryzen 3100 cost in the beginning? 110 Euro, one chiplet.
The cheapest 64 core EPYC I could find? 5400 Euro, or 675 per chiplet. 49 times more per CPU, and 6 times more per chiplet.

So it's probable that AMD makes more money from more expensive CPU's, even though EPYC most likely have higher manufacturing costs altogether.
Also, increasing the market share in the server world is considered important in the long run.

You don't have to like this, but it makes perfect sense as to why AMD does this. Add chip shortage and they have yet another reason.

Comparing the 5800X3D with non-existing budget CPU's doesn't make sense either, since the 5800X3D isn't a budget model.

 

[Jism]

This refinement is an answer to intels recently P/E core thing.

I'm glad to read the clocks are capable of doing beyond 5Ghz. Thats just amazing, 8 core 16 thread with an additional 64MB of L3 cache. And the stock Ryzen 5800X was already "twice" as fast as a 2700X.

Great upgrade.

 

[Minus Infinity]

So this cpu will be faster in clock speeds, consume less power and put out less heat than ryzen 7 5800X ? Is this what I'm suppose to understand.

I thought this is clocked lower than standard 5800X to keep power in check. It has the same TDP at the lower clocks because it is more power hungry due to the extra cache. You can OC it of course, but how well it does we don't know.

 

[ratirt]

If this 5800x3D will perform better than mine 5800x I might pull a trigger on this one. Maybe not from the start but it is nice to have something to go for. Obviously will wait for the reviews.
When is AMD releasing this thing?

 

[Tomorrow]

If this 5800x3D will perform better than mine 5800x I might pull a trigger on this one. Maybe not from the start but it is nice to have something to go for. Obviously will wait for the reviews.
When is AMD releasing this thing?

Spring. Im guessing April-May.

 

[stimpy88]

Cool tech, but very disappointed in the fact that it's only being used in a low-end gaming CPU.

 

[BHS1975]

Gonna be interesting to see how good it can be cooled with that cache chip on the top.

 

[Chomiq]

All I'm worried about is price.

Cool tech, but very disappointed in the fact that it's only being used in a low-end gaming CPU.

Since when 5800x is a low-end gaming CPU?

 

[stimpy88]

All I'm worried about is price.

Since when 5800x is a low-end gaming CPU?

Since I already have a 16 core CPU...