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AMD EPYC "Genoa" Zen 4 Processor Multi-Chip Module Pictured

btarunr

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Here is the first picture of a next-generation AMD EPYC "Genoa" processor with its integrated heatspreader (IHS) removed. This is also possibly the first picture of a "Zen 4" CPU Complex Die (CCD). The picture reveals as many as twelve CCDs, and a large sIOD silicon. The "Zen 4" CCDs, built on the TSMC N5 (5 nm EUV) process, look visibly similar in size to the "Zen 3" CCDs built on the N7 (7 nm) process, which means the CCD's transistor count could be significantly higher, given the transistor-density gained from the 5 nm node. Besides more number-crunching machinery on the CPU core, we're hearing that AMD will increase cache sizes, particularly the dedicated L2 cache size, which is expected to be 1 MB per core, doubling from the previous generations of the "Zen" microarchitecture.

Each "Zen 4" CCD is reported to be about 8 mm² smaller in die-area than the "Zen 3" CCD, or about 10% smaller. What's interesting, though, is that the sIOD (server I/O die) is smaller in size, too, estimated to measure 397 mm², compared to the 416 mm² of the "Rome" and "Milan" sIOD. This is good reason to believe that AMD has switched over to a newer foundry process, such as the TSMC N7 (7 nm), to build the sIOD. The current-gen sIOD is built on Global Foundries 12LPP (12 nm). Supporting this theory is the fact that the "Genoa" sIOD has a 50% wider memory I/O (12-channel DDR5), 50% more IFOP ports (Infinity Fabric over package) to interconnect with the CCDs, and the mere fact that PCI-Express 5.0 and DDR5 switching fabric and SerDes (serializer/deserializers), may have higher TDP; which together compel AMD to use a smaller node such as 7 nm, for the sIOD. AMD is expected to debut the EPYC "Genoa" enterprise processors in the second half of 2022.



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"(12-channel DDR5)"

I wonder how many mem channels the desktop version will have? 2 or 4?
 
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Looks to be a big step up from Zen 3. Analogous to the step up to Alder Lake for Intel.
 
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"(12-channel DDR5)"

I wonder how many mem channels the desktop version will have? 2 or 4?
I think it will still be 2 and 4 channels for a HEDT line up.

The reason to avoid going more than dual channel on desktop is to keep cost low. 2 Channels of DDR5 memory already provides alot of bandwidth.
 
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Looks to be a big step up from Zen 3. Analogous to the step up to Alder Lake for Intel.
AMD has said Zen 4 is the biggest architectural change to Zen since it's inception. It will be a bigger performance jump than Zen 2 -> Zen 3
 

btarunr

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"(12-channel DDR5)"

I wonder how many mem channels the desktop version will have? 2 or 4?
12-channel DDR5 implies 24 sub-channels. Alder Lake has 2-channel DDR5, or 4 sub-channels. So it's likely that Raphael will have the same 2-channel (4 sub-channel) DDR5 interface as Alder Lake.

1649637390523.png
 
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The reason to avoid going more than dual channel on desktop is to keep cost low. 2 Channels of DDR5 memory already provides alot of bandwidth.

But it would be so cool...

Now that they seem to have killed regular Threadripper imagine having a X690 chipset (nice :D ) besides the expected X670/B650 with quad channel support for a couple of the higher end CPUs (like the 7700x, 7900x and 7950x or whatever the names end up being)
 

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But it would be so cool...

Now that they seem to have killed regular Threadripper imagine having a X690 chipset (nice :D ) besides the expected X670/B650 with quad channel support for a couple of the higher end CPUs (like the 7700x, 7900x and 7950x or whatever the names end up being)
What would be nice is the SkT A days where the Server/Workstation CPUs were on the Same Socket as The lower models
 
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This proves that Genoa 96C/192T models are using 8C/16T CCDs, yet another nail in the coffin for the 16C/32T CCD theory.

They're not going to squeeze four CCDs in a neat line onto the SP5 package though, I'm guessing if there is no 16C CCD (why would AMD make a totally new die just for one product?) they'll just organise them in a 2x2 grid instead of a 4x1 line.

"(12-channel DDR5)"

I wonder how many mem channels the desktop version will have? 2 or 4?
There currently isn't a Threadripper for consumers, so you'll likely only see it as a Threadripper Pro in HP/Lenovo/Dell OEM board unless AlderLake-X prompts AMD to compete this generation rather than next.

In saying that, Threadripper has always been a minimum of 4-channels which was one of the main distinctions between Ryzen and Threadripper when core counts matched (so the 12C and 16C Threadrippers being otherwise pointless alongside the 3900X, 3950X, 5900X, 5950X)
 
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This proves that Genoa 96C/192T models are using 8C/16T CCDs, yet another nail in the coffin for the 16C/32T CCD theory.

They're not going to squeeze four CCDs in a neat line onto the SP5 package though, I'm guessing if there is no 16C CCD (why would AMD make a totally new die just for one product?) they'll just organise them in a 2x2 grid instead of a 4x1 line.


There currently isn't a Threadripper for consumers, so you'll likely only see it as a Threadripper Pro in HP/Lenovo/Dell OEM board unless AlderLake-X prompts AMD to compete this generation rather than next.

In saying that, Threadripper has always been a minimum of 4-channels which was one of the main distinctions between Ryzen and Threadripper when core counts matched (so the 12C and 16C Threadrippers being otherwise pointless alongside the 3900X, 3950X, 5900X, 5950X)
Genoa (and Genoa-X) was always suppose to be 12 8 cores CCD. It's Bergamo that is suppose to have the 16cores CCD. Those will be Zen4 core with less caches (rumours is smaller L2 and L3). Those will only be sold to Cloud provider if the rumors is true for now.

The rumors is also those 16c ccd will be the Little cores of Zen5 or at least based on those.

I don't think desktop right now need more than 2 channels, I think on die Cache will have much more significant performance gain overall for most memory sensitive application. Like people said, you have effectively 4 subchannel to interleave your memory request on DDR5 and that should be enough for standard desktop workload. DDR5 also allow higher capacity DIMM so we should be fine there too.

Soon the cost of adding 3d-vCache on the die will probably be smaller than making a motherboard with 2 extra channel+ having to buy 2 extra dimm.
 
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