Intel Planning a Return to HEDT with "Alder Lake-X"?

[lexluthermiester]

But AMD could have easily made TRX40 versions of 5800X/5900X, instead of planning the platform to start at 24 cores.

This. Very easily. And yet they didn't. Likewise, Intel could have easily done an expanded version of Socket 2066. And yet they didn't.

Irritating..

 

[efikkan]

This. Very easily. And yet they didn't. Likewise, Intel could have easily done an expanded version of Socket 2066. And yet they didn't.

Irritating..

Yes, and I would have happily paid $50+ extra for the CPU and $100+ for the motherboard for the HEDT features.

It's a bit more complicated for Intel though…

 

[lexluthermiester]

It's a bit more complicated for Intel though…

Not really. Minimal re-engineering & retooling for the new chipsets and CPU types.

 

[Rakhmaninov3]

9000 cores, 9000 TB/s, 9000 cache, 9000 pins, 9000 1000s of dollars

The Intel Yarnripper 9000

 

[efikkan]

Not really. Minimal re-engineering & retooling for the new chipsets and CPU types.

The chipsets are actually a no-brainer, even the workstation chips supports the smaller CPUs with the right BIOS (as proven by those third-party motherboards from China). But getting extra PCIe lanes etc. requires some engineering, and doing even "small" die changes quickly takes >1 year to enter the market, but still doable if planned in time. So unless I misunderstood you, it's not that trivial.

 

[lexluthermiester]

The chipsets are actually a no-brainer, even the workstation chips supports the smaller CPUs with the right BIOS (as proven by those third-party motherboards from China). But getting extra PCIe lanes etc. requires some engineering, and doing even "small" die changes quickly takes >1 year to enter the market, but still doable if planned in time. So unless I misunderstood you, it's not that trivial.

PCIe lanes are almost trivial as they can load up the chipset with a bunch for extended IO and thus keeping direct-to-CPU lanes grouped in the main PCIe slots. And realistically, when they're designing a new family/revision of CPUs, they have to design the chipset along side them. So again, trivial effort IF they make the effort. They didn't. Neither did AMD. That's on both companies for failing to see the need or having the foresight to appeal to the HEDT market segment.

 

[efikkan]

PCIe lanes are almost trivial as they can load up the chipset with a bunch for extended IO and thus keeping direct-to-CPU lanes grouped in the main PCIe slots.

It does not solve the problem when a CPU lacks sufficient CPU PCIe lanes.
And extra PCIe lanes through the chipset isn't sufficient for power users, as these share bandwidth. Not only can't you populate all of the PCIe, M.2, SATA ports at the same time, utilizing certain combinations of these will reduce the bandwidth left to the others.

And realistically, when they're designing a new family/revision of CPUs, they have to design the chipset a long side them. So again, trivial effort IF they make the effort. They didn't.

In most cases, they already are "compatible". Early development boards often are modified boards with the previous gen chipset.

 

[lexluthermiester]

It does not solve the problem when a CPU lacks sufficient CPU PCIe lanes.

True, but they would not have made an HEDT offering and skimped on the PCIe lanes, so that's not a concern.

And extra PCIe lanes through the chipset isn't sufficient for power users, as these share bandwidth.

While true, that doesn't mean they're useless.