AMD EPYC "Bergamo" 128-core Processor Based on Same SP5 Socket as "Genoa"

[btarunr]

AMD is launching two distinct classes of next-generation enterprise processors, the 4th Generation EPYC "Genoa" with CPU core-counts up to 96-core/192-thread; and the new EPYC "Bergamo" with a massive 128-core/256-thread compute density. Pictures of the "Genoa" MCM are already out in the wild, revealing twelve "Zen 4" CCDs built on 5 nm, and a new-generation sIOD (I/O die) that's very likely built on 6 nm. The fiberglass substrate of "Genoa" already looks crowded with twelve chiplets, making us wonder if AMD needed a larger package for "Bergamo." Turns out, it doesn't.

In its latest Corporate presentation, AMD reiterated that "Bergamo" will be based on the same SP5 (LGA-6096) package as "Genoa." This would mean that the company either made room for more CCDs, or the CCDs themselves are larger in size. AMD states that "Bergamo" CCDs are based on the "Zen 4c" microarchitecture. Details about "Zen 4c" are scarce, but from what we gather, it is a cloud-optimized variant of "Zen 4" probably with the entire ISA of "Zen 4," and power characteristics suited for high-density cloud environments. These chiplets are built on the same TSMC N5 (5 nm EUV) process as the regular "Zen 4" CCDs.



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[beautyless]

I heard from some YouTube channel that Zen4C is Zen4 increased to 16cores per chiplet, has lower L3 cache per core, full ISA, this comparable to E-cores of Intel.

Bergamo server might use 8xchiplet of this instead of 12. (For this, this is just my guest, no source)

 

[AnarchoPrimitiv]

I wonder if any of this will make it to more cores in the AM5 socket with Zen4, probably not. But, it'd be interesting if a package had one Zen4 chiplet and one Zen4c chiplet... 24 cores/48 threads? Then throw some V-cache in, haha

 

[beedoo]

I wonder if any of this will make it to more cores in the AM5 socket with Zen4, probably not. But, it'd be interesting if a package had one Zen4 chiplet and one Zen4c chiplet... 24 cores/48 threads? Then throw some V-cache in, haha

I hope they pull something special out of the bag as my old Threadripper 2950X is getting a bit old now; a 2018 build should have been upgraded last year...

 

[Crackong]

this comparable to E-cores of Intel.

E-core does not have the same ISA as the P-cores
Things running fine on P-cores might crash on e-cores.

But things running fine on Zen4 will run fine on Zen4c, just a bit slower without a larger cache.

 

[Tom Yum]

E-core does not have the same ISA as the P-cores
Things running fine on P-cores might crash on e-cores.

But things running fine on Zen4 will run fine on Zen4c, just a bit slower without a larger cache.

The other thing AMD could do is use higher density cell libraries for Zen4c, reducing the size and power requirements of each core but at the expense of reduced frequency scaling (and hence processing power). That way they can also maintain the same ISA, avoiding the issues Intel has with AVX512 support on Alder Lake, while still scaling down core size and power in order to scale up core count. Likely we'll see both, reduced L2/L3 cache and higher density cell libraries.

 

[Denver]

I heard from some YouTube channel that Zen4C is Zen4 increased to 16cores per chiplet, has lower L3 cache per core, full ISA, this comparable to E-cores of Intel.

Bergamo server might use 8xchiplet of this instead of 12. (For this, this is just my guest, no source)

Then the 3D cache enters the equation, fixing the deficiency if necessary to combat the avalanche of small cores that intel intends to use. Well done.

 

[Crackong]

Then the 3D cache enters the equation, fixing the deficiency if necessary to combat the avalanche of small cores that intel intends to use. Well done.

Current Zen3 CCD uses half of its die area for L3 cache
Imagine all of those areas can be ultilize to fit double the cores and L3 cache is just added by stacking V-cache vertically.
That means a 16 core CCD within the same area......

 

[Chrispy_]

Four CCDs in a row ain't gonna work in the same socket.

I guess they'll cluster them in 2x2 quads - something like this, though they'll probably do it more carefully than the 90 seconds it took me to photoshop that dog's dinner.

 

[Denver]

Current Zen3 CCD uses half of its die area for L3 cache
Imagine all of those areas can be ultilize to fit double the cores and L3 cache is just added by stacking V-cache vertically.
That means a 16 core CCD within the same area......

I don't think it's possible to drop all the L3 cache, then just add 3D cache on top. from what I saw the extra memory die is stacked above the normal cache.

 

[Chrispy_]

I don't think it's possible to drop all the L3 cache, then just add 3D cache on top. from what I saw the extra memory die is stacked above the normal cache.

View attachment 248909

Yep, I believe it was mentioned in the 3D-VCache announcement last year that a big reason they can stack above the existing cache is because cache logic generates less heat than the execution pipelines. If there was execution logic underneath instead of more cache, the thermals would be unmanageable without massively throttling the clockspeeds.

 

[Aquinus]

128-core/256-thread compute density

Imagine a two processor server having 512 logical threads. What a time to be alive.

 

[Wirko]

Imagine a two processor server having 512 logical threads. What a time to be alive.

Twelve memory channels (12 x 64 bits) may soon become a limiting factor in such big processors, depending on the application of course.

 

[btarunr]

Twelve memory channels (12 x 64 bits) may soon become a limiting factor in such big processors, depending on the application of course.

Genoa/Bergamo has 12-channel DDR5 (that's 24 x 40 bits).

 

[BorgOvermind]

Imagine a two processor server having 512 logical threads. What a time to be alive.

CPUs maybe are finally ending up using core architecture like GPUs use for years.