I don't exactly understand what you meant. TSMC has several modifications of the N7 production lines:
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7 nm process - Wikipedia
N6 is nothing but N7++.
I think it is mostly a nudge towards more efficiency while maintaining / slightly improving the density. More EUV less DUV, or fewer masks/layers.
The advantages cannot be understated, because fewer steps towards a full chip is a boost to yields and to quality of the silicon. So an N6 process might very well clock a lot higher, for example. Its not just about density, its about consistency.
Take note of the power envelope on Intel's '7'. Its not pretty, it won't really clock that well above 4.8~5.0 Ghz. And it took them a LONG time to get there, even so, when they do, its grossly inefficient.
Similarly, compare TSMC's 7nm GPUs (AMD) versus Nvidia's Samsung 8nm GPUs. The former is built up out of (part) EUV. The latter is DUV. We're looking at gaps of 500mhz and more. The TL DR here is that even if you 'shrink' chips based on DUV patterning they won't quite work as you'd want. Its clearly the end of DUV to facilitate further 'true' shrinks that make economical sense.
That is in a nutshell, the whole reason Intel stagnated beyond 14nm. Going smaller on DUV is absolute hell. And it is why Intel is moving as it does today. They saw what TSMC realised first, and have admitted defeat by embracing EUV, and even pushing it harder than TSMC wrt testing new aperture sizes and stuff. They want that node advantage again.