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Intel Unintentionally Shares 700-Series Chipset Spec

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AFAIK, TB4 is not 100% the same as USB4. For instance, even though both are 40Gbit/s, TB4 can only utilize 32Gbit/s for data transfers (8Gbit/s is reserved for video), plus has higher overhead so the real world data transfers are around 22Gbit/s. USB4 can utilize full 40Gbit/s for data transfers with less overhead - around 5Gbit/s = 35Gbit/s transfer speeds from and to PC using USB4 vs. 22 Gbit/s TB4.
Source: https://www.tripplite.com/products/thunderbolt-4

Also, TB4 has 100W power delivery, USB4 with Extended power range is capable to deliver up to 240W.
Source: https://en.wikipedia.org/wiki/USB4#Data_transfer_modes
Of course TB4 is not the same as USB4. I did not say that at any moment.

On TB4, PCIe 3.0 transfer speed is just shy of ~3 GB/s, which is similar to good NVMe drives running at 3.0 speed x4 in external enclosure with TB4 chip and interface. The main difference is that PCIe 3.0 x4 is obligatory on TB4, whereas on USB4 host device 40 Gbps link, PCIe and TB Alt tunneling are only optional, so OEMs have three choices:
1. install Maple Ridge TB4 chip on either Intel or AMD motherboards to get all features above - cost up
2. install minimal USB4 chip for Rembrandt APUs with 20 Gbps link - PD 3.0/3.1, USB data 10 Gbps, DP 1.4 tunneling and DP Alt minimum 1.4
3. install full fat USB4 chip for Rembrandt APUs with 40 Gbps link - PD 3.0/3.1, USB data 20 Gbps, PCIe data, DP 1.4 tunneling and DP 2.0 Alt at 40 Gbps
* it should be checked whether both USB4 controllers are available. I have only seen VL830 for hubs, which does not support PCIe.

Also, if OEMs decide to tunnel PCIe data over USB4, they need to wire it, which is usually 3.0 x4 or 4.0 x4. So, PCIe over one USB4 port will effectively be at 32 Gbps with overhead and not 40 Gbps, or 64 Gbps split between two ports (some laptops with Rembrandt APUs).

*For Rembrandt APU, PCIe 4.0 wiring for USB4 is x4. APUs have x4 general purpose 4.0 lanes, so x2 for one USB4 port or x4 for two USB4 ports, if OEMs certify one or two ports and add PCIe tunneling. Those APUs also support DP 2.0 at 40 Gbps on die. If all features are implemented, this would be "TB4 plus", due to DP 2.0 and PCIe 4.0. Intel is aiming to match and surpasss this with TB5, where DP 2.0 will have 80 Gbps.
Current evolution of high-speed, multi interface looks like this:
1. TB4 chip - PCIe 3.0 at 32 Gbps, USB 10 Gbps, DP 1.4 at 32 Gbps and PD 3.0 100W+15W, can tunnel two displays
2. USB4 chip-PCIe 4.0 at 64 Gbps (two ports, each 32), USB 20 Gbps, DP 1.4 tunnel at 32 Gbps, DP 2.0 Alt at 40 Gbps and PD 3.1 up to 240W, can tunnel one display
3. TB5 chip - PCIe 5.0 at 128 Gbps (two ports, each 64), USB 20 Gbps, DP 2.0 host at 80 Gbps and PD 3.1 240W, can tunnel two or more displays

* For TB5 chips on desktop PC, Intel would first need to enable PCIe 5.0 lanes on DMI link and in the chipset, so that TB5 chips can take advantage. Not on Z790 platform. They will first enable TB5 on die for laptop CPUs starting with Meteor Lake or later, as their CPUs support PCIe 5.0. Step by step.

Recent power delivery PD 3.1 revision indeed introduced up to 240W, but this is highly unlikely to be found in any PC desktop host. This solution is for laptops and docking stations/hubs, whereas charging from USB4 port on desktop host will mostly be limited to PD 3.0 chips, up to 100W. It seems that 240W of charging power on desktop motherboard could only be on rare halo models, as it will drive costs to isolate heat.

My point is just that on the intel desktop side, TB4 support is optional and not embedded into the cpu or chipset. There still must be a discrete TB4 solution which is offered on some but not all SKUs.
True. On desktop, not all motherboards need TB4 chips and it is right to leave it to OEMs to decide, depending on market they target with specific motherboards.

If however USB4 (or TB4) was embedded into the chipset or cpu then it would be a standard feature of z790. Instead, the standard usb-c solution of intel Z chipsets (Z590, Z690, and now Z790) is USB3.2x2 which is 20 Gbps but differs from USB4 in that it doesn’t support PCIe tunneling. So the native solution is kind of useless in my opinion. Because most storage devices top out at usb3 10 gbps… and if your usb-c device uses PCIE tunneling (nvme storage, 10gbps lan adapter, audio interface, egpu) then you still need TB. So from my point of view, 1 guaranteed USB4 port would be great… instead you have to shell more $$$ for a mobo with TB4 (maple ridge).
True. USB Implementers Forum came to compromize with OEMs and did not mandate PCIe tunneling. They also wanted USB4 to be a bit different from TB. Intel mainstream desktop CPUs do not support USB from processors, only from chipset. AMD CPUs do and it is easier for Ryzen to support USB4 from CPU.

Z790 chipset could add USB4 natively, but this remains to be seen, as they already have TB4 chips and TB5 is in development.

Given the optional nature of TB4 (and thus USB4) on Intel chipsets, I was simply wondering how AMD will implement USB4 on its upcoming chipset. Whether it will be standard unlike on Intel. Don’t know. Waiting to see.
USB4 is already supported on Rembrandt platform, if OEMs decide to install a controller. So, up to 40 Gbps, could pair with PCIe 4.0 GPP and DP 2.0 Alt Mode and DP 1.4 tunneling form iGPU. This will also come to Zen 4 platform. It's a full scale USB4 enablement, but only on certified devices and if OEMs decide to utilize it. CPU is fully capable for USB4 and DP 2.0. It remains to be seen which OEMs decide to implement it, and how.

And the other issue is prior to Titan ridge, Intel TB solutions did not have a USB3.x fallback mode. Meaning that with an Alpine ridge controller for example (which is the controller of choice in many external nvme solutions) if you plug the device into a standard usb 3.x port, it doesn’t function. But it would function if plugged into a USB4 port (because of backwards compatibility with TB3). So even with the usb3.2x2 port on Z690 or z90, it is useless if you connect an Alpine Ridge device to it.
That was unfortunate, but predicted by the spec.
JHL6240 chip provided USB downstream port, without compatibility for USB devices.
JHL6340 chip provided USB host port compatible for USB devices.
JHL6540 chip provided both host port and downstream port from peripherals that support USB devices, but are more expensive.

JHL6240 is the cheapest chip. I am not surprised that NVMe external storage vendors install this one. They should clearly say to buyers that connecting such device with USB port on the host system will not work if the host system does not have at least the same TB3 chip.
 
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Of course TB4 is not the same as USB4. I did not say that at any moment.

On TB4, PCIe 3.0 transfer speed is just shy of ~3 GB/s, which is similar to good NVMe drives running at 3.0 speed x4 in external enclosure with TB4 chip and interface. The main difference is that PCIe 3.0 x4 is obligatory on TB4, whereas on USB4 host device 40 Gbps link, PCIe and TB Alt tunneling are only optional, so OEMs have three choices:
1. install Maple Ridge TB4 chip on either Intel or AMD motherboards to get all features above - cost up
2. install minimal USB4 chip for Rembrandt APUs with 20 Gbps link - PD 3.0/3.1, USB data 10 Gbps, DP 1.4 tunneling and DP Alt minimum 1.4
3. install full fat USB4 chip for Rembrandt APUs with 40 Gbps link - PD 3.0/3.1, USB data 20 Gbps, PCIe data, DP 1.4 tunneling and DP 2.0 Alt at 40 Gbps
* it should be checked whether both USB4 controllers are available. I have only seen VL830 for hubs, which does not support PCIe.

Also, if OEMs decide to tunnel PCIe data over USB4, they need to wire it, which is usually 3.0 x4 or 4.0 x4. So, PCIe over one USB4 port will effectively be at 32 Gbps with overhead and not 40 Gbps, or 64 Gbps split between two ports (some laptops with Rembrandt APUs).

*For Rembrandt APU, PCIe 4.0 wiring for USB4 is x4. APUs have x4 general purpose 4.0 lanes, so x2 for one USB4 port or x4 for two USB4 ports, if OEMs certify one or two ports and add PCIe tunneling. Those APUs also support DP 2.0 at 40 Gbps on die. If all features are implemented, this would be "TB4 plus", due to DP 2.0 and PCIe 4.0. Intel is aiming to match and surpasss this with TB5, where DP 2.0 will have 80 Gbps.
Current evolution of high-speed, multi interface looks like this:
1. TB4 chip - PCIe 3.0 at 32 Gbps, USB 10 Gbps, DP 1.4 at 32 Gbps and PD 3.0 100W+15W, can tunnel two displays
2. USB4 chip-PCIe 4.0 at 64 Gbps (two ports, each 32), USB 20 Gbps, DP 1.4 tunnel at 32 Gbps, DP 2.0 Alt at 40 Gbps and PD 3.1 up to 240W, can tunnel one display
3. TB5 chip - PCIe 5.0 at 128 Gbps (two ports, each 64), USB 20 Gbps, DP 2.0 host at 80 Gbps and PD 3.1 240W, can tunnel two or more displays

* For TB5 chips on desktop PC, Intel would first need to enable PCIe 5.0 lanes on DMI link and in the chipset, so that TB5 chips can take advantage. Not on Z790 platform. They will first enable TB5 on die for laptop CPUs starting with Meteor Lake or later, as their CPUs support PCIe 5.0. Step by step.

Recent power delivery PD 3.1 revision indeed introduced up to 240W, but this is highly unlikely to be found in any PC desktop host. This solution is for laptops and docking stations/hubs, whereas charging from USB4 port on desktop host will mostly be limited to PD 3.0 chips, up to 100W. It seems that 240W of charging power on desktop motherboard could only be on rare halo models, as it will drive costs to isolate heat.


True. On desktop, not all motherboards need TB4 chips and it is right to leave it to OEMs to decide, depending on market they target with specific motherboards.


True. USB Implementers Forum came to compromize with OEMs and did not mandate PCIe tunneling. They also wanted USB4 to be a bit different from TB. Intel mainstream desktop CPUs do not support USB from processors, only from chipset. AMD CPUs do and it is easier for Ryzen to support USB4 from CPU.

Z790 chipset could add USB4 natively, but this remains to be seen, as they already have TB4 chips and TB5 is in development.


USB4 is already supported on Rembrandt platform, if OEMs decide to install a controller. So, up to 40 Gbps, could pair with PCIe 4.0 GPP and DP 2.0 Alt Mode and DP 1.4 tunneling form iGPU. This will also come to Zen 4 platform. It's a full scale USB4 enablement, but only on certified devices and if OEMs decide to utilize it. CPU is fully capable for USB4 and DP 2.0. It remains to be seen which OEMs decide to implement it, and how.


That was unfortunate, but predicted by the spec.
JHL6240 chip provided USB downstream port, without compatibility for USB devices.
JHL6340 chip provided USB host port compatible for USB devices.
JHL6540 chip provided both host port and downstream port from peripherals that support USB devices, but are more expensive.

JHL6240 is the cheapest chip. I am not surprised that NVMe external storage vendors install this one. They should clearly say to buyers that connecting such device with USB port on the host system will not work if the host system does not have at least the same TB3 chip.
You’re quite Knowledgeable about thunderbolt! Cool beans. I’m looking forward to TB5.
 
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You’re quite Knowledgeable about thunderbolt! Cool beans. I’m looking forward to TB5.
Thank you. It's a rabbit hole of confusing specs, incompatibilities, dubious marketing and silence from vendors on what is supported and what is not supported...
I needed to learn more to avoid mistakes in future.

The bottom line for current Thunderbolt connections is that it is good for 10 GbE networking on 2 metre distance with copper cable and for external storage and hubs.

Thunderbolt is not good for monitors as it still does not support VRR/Gsync/FreeSync pass-through, and most adapter cables do not support it either. Intel's TB spec does not explicitly state that TB chip supports AdaptiveSync from DP spec. Finally, Gsync and FreeSync work over DP (including usb-c) and HDMI interfaces only.

Do not hold your breath for TB5 paired with monitors. To support variable refresh rate, gaming community needs to openly challenge Intel to implement it. Even Apple has problems with AdaptiveSync in their ecosystem over tunnelled DP inside TB. Apple will aim to enable full USB4 to get their head around it. "Fully-fat" USB4 implementation can work better than Thunderbolt.
 
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Is this chipset going to support USB 4.0, or not yet?
 
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