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Intel's future Meteor Lake APUs seem to be playing catch-up to AMD's integrated graphics in more ways than one. Twitter user Coelacanth's Dream has dug up information that indicates Intel's commitment to bring ray tracing support to even its IGP (Integrated Graphics Processing) tiles. According to bits and pieces from Intel Graphics Compiler (IGC) code patches, it seems to be confirmed that ray tracing support is indeed coming to the TSMC-made, 3 nm GPU tiles in Meteor Lake. The kicker here is the presence of flags that detect whether the iGPU is of the "iGFX_meteorlake" type - if so, IGC sets ray tracing support to enabled.
Puzzlingly, Intel's upscaling technology, Xe SuperSampling (XeSS) could be out of the picture - at least for now. It seems that IGC patches for the upcoming APU family still don't allow for DPAS (Dot Product Accumulate Systolic) instructions - instructions that rely on XMX (Intel Xe Matrix Extensions), the AI engines responsible for executing 128 FP16/BF16, 256 INT8, or 512 INT4/INT2 operations per clock. These low-precision operations are the soul of algorithmic supersampling technologies such as XeSS.
It seems strange that Intel would go out of its way to enable ray tracing on its APUs, which will necessarily feature few of the corresponding hardware accelerators due to die size constraints (limiting ray tracing performance), rather than using that same space for XMX accelerators, which could help improve performance through access to XeSS. Of course, these are all bits and pieces gleaned from IGC, and Intel still has work ahead before Meteor Lake ever hits the market.
Considering Intel's recent execution woes, it remains to be seen if Meteor Lake will see the light of day in or around its planned launch. A cadre of new technologies are being integrated at the same time - such as the CPU tile, which is being manufactured in Intel's new manufacturing process, Intel 4. The GPU tile itself has been confirmed by Intel to make use of TSMC's 3 nm manufacturing process, but all may not be well over at graphics land; it seems that Intel has elected to stop GPU tile production at the 3 nm process on TSMC's foundries. Speculation places Intel as electing to move the manufacturing process towards the more performant and power-efficient TSMC N3E process, which could make sense considering power efficiency requirements of APU designs.
View at TechPowerUp Main Site | Source
Puzzlingly, Intel's upscaling technology, Xe SuperSampling (XeSS) could be out of the picture - at least for now. It seems that IGC patches for the upcoming APU family still don't allow for DPAS (Dot Product Accumulate Systolic) instructions - instructions that rely on XMX (Intel Xe Matrix Extensions), the AI engines responsible for executing 128 FP16/BF16, 256 INT8, or 512 INT4/INT2 operations per clock. These low-precision operations are the soul of algorithmic supersampling technologies such as XeSS.
It seems strange that Intel would go out of its way to enable ray tracing on its APUs, which will necessarily feature few of the corresponding hardware accelerators due to die size constraints (limiting ray tracing performance), rather than using that same space for XMX accelerators, which could help improve performance through access to XeSS. Of course, these are all bits and pieces gleaned from IGC, and Intel still has work ahead before Meteor Lake ever hits the market.
Considering Intel's recent execution woes, it remains to be seen if Meteor Lake will see the light of day in or around its planned launch. A cadre of new technologies are being integrated at the same time - such as the CPU tile, which is being manufactured in Intel's new manufacturing process, Intel 4. The GPU tile itself has been confirmed by Intel to make use of TSMC's 3 nm manufacturing process, but all may not be well over at graphics land; it seems that Intel has elected to stop GPU tile production at the 3 nm process on TSMC's foundries. Speculation places Intel as electing to move the manufacturing process towards the more performant and power-efficient TSMC N3E process, which could make sense considering power efficiency requirements of APU designs.
View at TechPowerUp Main Site | Source