Samsung Electronics Unveils Plans for 1.4 nm Process Technology

[btarunr]

Samsung Electronics, a world leader in advanced semiconductor technology, announced today a strengthened business strategy for its Foundry Business with the introduction of cutting-edge technologies at its annual Samsung Foundry Forum event. With significant market growth in high-performance computing (HPC), artificial intelligence (AI), 5/6G connectivity and automotive applications, demand for advanced semiconductors has increased dramatically, making innovation in semiconductor process technology critical to the business success of foundry customers. To that end, Samsung highlighted its commitment to bringing its most advanced process technology, 1.4-nanometer (nm), for mass production in 2027.

During the event, Samsung also outlined steps its Foundry Business is taking in order to meet customers' needs, including: foundry process technology innovation, process technology optimization for each specific applications, stable production capabilities, and customized services for customers. "The technology development goal down to 1.4 nm and foundry platforms specialized for each application, together with stable supply through consistent investment are all part of Samsung's strategies to secure customers' trust and support their success," said Dr. Si-young Choi, president and head of Foundry Business at Samsung Electronics. "Realizing every customer's innovations with our partners has been at the core of our foundry service."



Showcasing Samsung's Advanced Node Roadmap Down to 1.4 nm in 2027
With the company's success of bringing the latest 3 nm process technology to mass production, Samsung will be further enhancing gate-all-around (GAA) based technology and plans to introduce the 2 nm process in 2025 and 1.4 nm process in 2027.

While pioneering process technologies, Samsung is also accelerating the development of 2.5D/3D heterogeneous integration packaging technology to provide a total system solution in foundry services.

Through continuous innovation, its 3D packaging X-Cube with micro-bump interconnection will be ready for mass production in 2024, and bump-less X-Cube will be available in 2026.

Proportion of HPC, Automotive and 5G to be More than 50% by 2027
Samsung actively plans to target high-performance and low-power semiconductor markets such as HPC, automotive, 5G and the Internet of Things (IoT).

To better meet customers' needs, customized and tailored process nodes were introduced during this year's Foundry Forum. Samsung will enhance its GAA-based 3 nm process support for HPC and mobile, while further diversifying the 4 nm process specialized for HPC and automotive applications.

For automotive customers specifically, Samsung is currently providing embedded non-volatile memory (eNVM) solutions based on 28 nm technology. In order to support automotive-grade reliability, the company plans to further expand process nodes by launching 14 nm eNVM solutions in 2024 and adding 8 nm eNVM in the future. Samsung has been mass producing 8 nm RF following 14 nm RF, and 5 nm RF is currently in development.

"Shell-First" Operation Strategy to Respond to Customer Needs in a Timely Manner
Samsung plans to expand its production capacity for the advanced nodes by more than three times by 2027 compared to this year.

Including the new fab under construction in Taylor, Texas, Samsung's foundry manufacturing lines are currently in five locations: Giheung, Hwaseong, and Pyeongtaek in Korea; and Austin and Taylor in the United States.

At the event, Samsung detailed its "Shell-First" strategy for capacity investment, building cleanrooms first irrespective of market conditions. With cleanrooms readily available, fab equipment can be installed later and set up flexibly as needed in line with future demand. Through the new investment strategy, Samsung will be able to better respond to customers' demands.

Investment plans in a new "Shell-First" manufacturing line in Taylor, following the first line announced last year, as well as potential expansion of Samsung's global semiconductor production network were also introduced.

Expanding the SAFE ecosystem to strengthen customized services
Following the "Samsung Foundry Forum," Samsung will hold the "SAFE Forum'"(Samsung Advanced Foundry Ecosystem) on October 4th. New foundry technologies and strategies with ecosystem partners will be introduced encompassing areas such as Electronic Design Automation (EDA), IP, Outsourced Semiconductor Assembly and Test (OSAT), Design Solution Partner (DSP) and the Cloud.

In addition to 70 partner presentations, Samsung Design Platform team leaders will introduce the possibility of applying Samsung's processes such as Design Technology Co-Optimization for GAA and 2.5D/3DIC.

As of 2022, Samsung provides more than 4,000 IPs with 56 partners, and is also cooperating with nine and 22 partners in the design solution and EDA, respectively. It also offers cloud services with nine partners and packaging services with 10 partners.

Along with its ecosystem partners, Samsung provides integrated services that support solutions from IC design to 2.5D/3D packages.

Through its robust SAFE ecosystem, Samsung plans to identify new fabless customers by strengthening customized services with improved performance, rapid delivery and price competitiveness, while actively attracting new customers such as hyperscalers and start-ups.

Starting in the United States (San Jose) on October 3rd, the "Samsung Foundry Forum" will be sequentially held in Europe (Munich, Germany) on the 7th, Japan (Tokyo) on the 18th, and Korea (Seoul) on the 20th, through which customized solutions for each region will be introduced. A recording of the event will be available online from the 21st for those who were unable to attend in person.

View at TechPowerUp Main Site

 

[gmn17]

Moore's Law marches on
Moore's Law Lives

 

[Prima.Vera]

What the 1.4nm does even mean anymore? Transistor size? Distance between transistors' gates? Look like this number has become more like a marketing number than actual science fact.

 

[Wirko]

The secret formula, in the last decade or so, has been this one: Add ~30 and you get the real nanometers.

 

[Flanker]

What the 1.4nm does even mean anymore? Transistor size? Distance between transistors' gates? Look like this number has become more like a marketing number than actual science fact.

Size of their shareholders' appendages

 

[Denver]

What the 1.4nm does even mean anymore? Transistor size? Distance between transistors' gates? Look like this number has become more like a marketing number than actual science fact.

It's just a smaller number to use as marketing against the competitor, nothing more... in general Samsung has a lot of problems even with the current lithography, for example 4nm is much worse than TSMC's 5nm, just look at the Snapdragon 8G1 vs. 8G1+, even with higher clockrate the latter being produced by tsmc is much more efficient

 

[Tropick]

Looking forward to the grand unveiling of the 1.4^(-.0493)nm node

Seriously when are we going to ditch the "nm" designation and move to a descriptor that's more... descriptive? Maybe transistor density per square millimeter? Because right now nm might as well stand for "no meaning" in terms of being tied to a real world metric.

 

[Wirko]

Looking forward to the grand unveiling of the 1.4^(-.0493)nm node

Seriously when are we going to ditch the "nm" designation and move to a descriptor that's more... descriptive? Maybe transistor density per square millimeter? Because right now nm might as well stand for "no meaning" in terms of being tied to a real world metric.

It's more fun if you believe in karma. Mr. Gelsinger, Dr. C. C. Wei of TSMC and Dr. Si-young Choi will be humans in their next incarnation, about 180,000,000 nanometers tall. Their kind of nanometers.

 

[trsttte]

Looking forward to the grand unveiling of the 1.4^(-.0493)nm node

Seriously when are we going to ditch the "nm" designation and move to a descriptor that's more... descriptive? Maybe transistor density per square millimeter? Because right now nm might as well stand for "no meaning" in terms of being tied to a real world metric.

Intel tried but no one went for it and after getting hammered by supposedly being way behind in process technology they joined the bullshit and renamed their nodes.

 

[Minus Infinity]

Keep announcing smaller nodes while you can't even produce great 8nm, 6nm, or 5nm nodes. Point to one feature that will be 1.4nm in size, not even line traces.

 

[Readlight]

Samsung always puts inside bloated battery's

 

[Wirko]

Does anybody know if Samsung is still in any kind of alliance with IBM in developing semiconductor technology?

Keep announcing smaller nodes while you can't even produce great 8nm, 6nm, or 5nm nodes. Point to one feature that will be 1.4nm in size, not even line traces.

Traces indeed not. But IBM showed the cross section of their "2 nm" chip and the thickness of one of the layers is actually around 2 nm. It's the layer of insulation around the fins or something like that, certainly not what IBM (or anyone else) is trying to advertise.

Intel tried but no one went for it and after getting hammered by supposedly being way behind in process technology they joined the bullshit and renamed their nodes.

During the complex, leading-edge process of renaming, the unit of measure got lost somewhere, and was never found again. Seven Intels it is now. Four Intels when it becomes a bit smaller.

 

[trsttte]

During the complex, leading-edge process of renaming, the unit of measure got lost somewhere, and was never found again. Seven Intels it is now. Four Intels when it becomes a bit smaller.

They'll have the unit again in a couple years when they reach Angstroms and given that everyone made the unit meaningless might as well not mention it, might incentivize people to instead look at metrics that actually matter like transistor density for example

 

[Wirko]

They'll have the unit again in a couple years when they reach Angstroms and given that everyone made the unit meaningless might as well not mention it, might incentivize people to instead look at metrics that actually matter like transistor density for example

This is long but worth reading, like everything David Kanter has written:

Transistor Count: A Flawed Metric

Transistor count and transistor density are often portrayed as technical achievements and milestones. Many vendors brag about the complexity of their design, as measured by transistor count. In reality, transistor count and density varies considerably based on the type of chip and especially the...

www.realworldtech.com

Using transistor density, there's probably less room for cheating for everyone involved but it's still far from a fair comparison. Manufacturers would have to agree on some standards, which they won't. Here's just one issue out of many: a transistor in a high-performance functional block is usually made larger than one in a low-power block, even if the manufacturing process is the same.
So the best you can get in way of density is probably the surface area of a standard 6-transistor SRAM cell that's used to make cache. The area has been published for every process node by every manufacturer. But SRAM cells with fewer or more transistors exist, and every one of them is a different kind of compromise.