Andes Technology Unveils The AndesCore AX60 Series, An Out-Of-Order Superscalar Multicore RISC-V Processor Family

[TheLostSwede]

Today, at Linley Fall Processor Conference 2022, Andes Technology, a leading provider of high efficiency, low power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, reveals its top-of-the-line AndesCore AX60 series of power and area efficient out-of-order 64-bit processors. The family of processors are intended to run heavy-duty OS and applications with compute intensive requirements such as advanced driver-assistance systems (ADAS), artificial intelligence (AI), augmented/virtual reality (AR/VR), datacenter accelerators, 5G infrastructure, high-speed networking, and enterprise storage.

The first member of the AX60 series, the AX65, supports the latest RISC-V architecture extensions such as the scalar cryptography extension and bit manipulation extension. It is a 4-way superscalar with Out-of-Order (OoO) execution in a 13-stage pipeline. It fetches 4 to 8 instructions per cycle guided by highly accurate TAGE branch predictor with loop prediction to ensure fetch efficiency. It then decodes, renames and dispatches up to 4 instructions into 8 execution units, including 4 integer units, 2 full load/store units, and 2 floating-point units. Besides the load/store units, the AX65's aggressive memory subsystem also includes split 2-level TLBs with multiple concurrent table walkers and up to 64 outstanding load/store instructions.




AX65 supports multicore cluster with cache coherence to scale out performance. Each core has 64 KB private instruction and data caches. The cluster contains up to 8 cores, an in-cluster coherence manager and a shared cache up to 8 MB. Its IO coherence interface keeps all AX65 caches coherent with respect to the external IO transactions and allows ease of SoC integration. The coherence manager and the shared cache can use a clock asynchronous to the cores for overall performance optimization in SoC implementations. Moreover, AX65 supports RISC-V standard external debug and instruction trace interfaces to facilitate fast system development, analysis and debugging.

"With hundreds of licensees and billions of chips embedding AndesCore, Andes has proved it as the CPU IP vendor to rely on. Our mission is to continue to provide a comprehensive lineup of processor IPs to support a wide range of applications from tiny MCUs to datacenter accelerators, offer efficient control processing as well as powerful compute acceleration, and run bare metal, RTOSes and Linux. We are excited to announce our top-of-the-line family of processors, the AX60 series, to further expand our portfolio. " said Dr. Charlie Su, President and CTO of Andes Technology. "The AX65 is to offer 2x performance in large benchmarks over the previous high-end core, the AX45, at the same frequency. In addition, it is capable of operating at 2.5 GHz at 7 nm process, 25% over the AX45. With the great boost in performance, the AX65 processor addresses the emerging requirements of a wide range of applications looking to raise control processor performance in the current high-performance SoCs."

The AndesCore AX65 is to be available for lead customers in mid-2023 through the early access program and for general customers by the end of the same year.

View at TechPowerUp Main Site | Source

 

[Scrizz]

nice

 

[stuarch]

Hope to see there are real competitions instead of "different" Cortex-X Cores.

 

[mplayerMuPDF]

this is looking great. Now we need a motherboard or SBC with at least 4 of these cores and decent IO priced at <$500 and the dream of an affordable enthusiast RISC-V system will have come true. It doesn't even have to be an ATX motherboard with GPU compatible PCIe slot or to have a beefy iGPU. If I could run it as a headless system that I can SSH into from one of my laptops that would already be great as long as it has good IO (a modest amount of PCIe, M.2 SATA/NVMe slots and SATA ports and solid USB).