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Eliyan Corporation, credited for the invention of the semiconductor industry's highest-performance and most efficient chiplet interconnect, today announced two major milestones in the commercialization of its technology for multi-die chiplet integration: the close of its Series A $40M funding round, and the successful tapeout of its technology on an industry standard 5-nanometer (nm) process.
Eliyan's NuLink PHY and NuGear technologies address the critical need for a commercially viable approach to enabling high performance and cost-effectiveness in the connection of homogeneous and heterogenous architectures on a standard, organic chip substrate. It has proven to achieve similar bandwidth, power efficiency, and latency as die-to-die implementations using advanced packaging technologies, but without the other drawbacks of specialized approaches.
Eliyan's chiplet packaging method is key to realizing the scale of performance and integration required in a broad range of compute intensive applications for data centers, cloud computing, AI and graphics.
The company's founding CEO Ramin Farjadrad is the inventor of the innovative and proven Bunch of Wires (BoW) scheme, which has been adopted by the Open Compute Project (OCP). NuLink technology is backward compatible with Universal Chiplet Interconnect Express (UCIe), a standard developed by Intel and donated to the UCIe Consortium, which includes 80+ leaders in semiconductor, packaging, foundries, cloud services and IP suppliers. Farjadrad's experience includes pioneering work in creating connectivity technologies such as PAM4 SerDes, Multi-Gbps Enterprise Ethernet, and Multi-Gbps Automotive Ethernet that were eventually adopted as IEEE Standards.
Eliyan's Series A round was led by Tracker Capital Management ("Tracker Capital"), which was founded by Stephen A. Feinberg, Co-Founder and Co-Chief Executive Officer of Cerberus Capital Management, L.P. Celesta Capital and other strategic investors including Intel Capital and Micron also participated. As part of the investment from Tracker Capital, made in February 2022, Dr. Shaygan Kheradpir of Cerberus, former Group CIO and a founding member of the Executive Leadership Committee at Verizon, will join the Board of Directors of Eliyan.
Funding supports accelerated validation and commercial readiness
Funding and support from leading industry players enable fast-track design, testing, and implementation ramp-up, culminating with the demonstration of the commercial readiness of Eliyan's best-in-class chiplet interconnect technology in a recent, successful tapeout using TSMC's 5 nm process. The design confirms Eliyan's ability to achieve twice the bandwidth at less than half the power consumption of current interconnect methods and does so using a standard system-in-package (SIP) manufacturing and packaging process. The ability to implement chiplet-based systems in organic packages enables the creation of larger and higher performance solutions at considerably lower power and cost of materials. These factors provide major gains in sustainability.
The company's first silicon is expected in the first quarter of 2023.
"Technology scaling using conventional system on chip (SoC) architectures is hitting the wall, requiring a new approach in how we integrate and manufacture silicon. Our extensive background in developing bleeding-edge technologies in this space led us to focus on a key challenge: interconnect improvements for system-in-package and chip-to-memory architectures as the path to deliver performance scaling," said Eliyan CEO and co-founder, Ramin Farjadrad. "Our approach supports and is compliant with the overall industry move toward chiplet-optimized interconnect protocols, including the UCIe standard as well as High Bandwidth Memory (HBM) protocols. This financial investment by industry leaders and the successful implementation of our design in 5 nm validates our strategy and prepares us for broader commercialization efforts."
Dr. Shaygan Kheradpir of Cerberus commented: "Traditional methods of integrating multi-chip architectures impose challenges that result in high costs, low yield, manufacturing complexity, and size limitations. Eliyan has drawn upon its years of experience to develop a practical scheme that is also backward compatible with existing standards to chiplet interconnect and is optimized for delivering the necessary high bandwidth, low latency, and low power capabilities. We are confident its NuLink technology holds the key to a broader proliferation of chiplets in key market sectors such as hyperscalers, AI processor development, high-performance memory, and advanced graphics chips."
Advanced chiplet interconnect is key to extending Moore's Law
Ulitlizing the manufacturing and cost advantages of chiplets, product developers can continue to scale the performance, power efficiency and size required by high performance computing applications. Industry forecasters estimate the chiplet sector of the semiconductor market will be $50B, with high-bandwidth memory (HBM) applications representing an additional $8B market growing at 50% CAGR.
Eliyan's innovative approach to connecting multi-die chip architectures is achieved without the need for complex and advanced packaging solutions such as silicon interposers. This is essential to cost-effectively leveraging the potential of the fast-growing chiplet-based architectures that experts agree are the pathway to extend Moore's Law.
A track record of interconnect innovation to enable the chiplet ecosystem
Eliyan's BoW approach was specifically developed to address the need for highly efficient die-to-die (D2D) PHYs to connect different functions in one package.
Its NuLink technology, which is a superset of BoW and UCIe, is an innovative PHY technology that uses patented implementation techniques to provide major power-performance differentiation for die-to-die (D2D) connectivity over any packaging substrate, reducing complexity and lowering overall development time and costs. It eliminates the need for advanced packaging solutions, such as silicon interposers that limit overall system-in-package size that ultimately limits performance, results in low wafer test coverage that ultimately impacts yield, increases total cost of ownership, and extends overall manufacturing cycle time.
The company's patented NuGear is an optimized technology for 2.5/3D implementations that enables practical mix and match of chiplets with different die-to-die interfaces in in different processes (DRAM, SOI, etc.).
The technology has been under development by Farjadrad and his team since 2017. In 2018, Farjadrad proposed BoW as a superior chiplet interconnect architecture to OCP. Given the significantly improved performance and features that BoW offered over existing methods, it received strong support and later was adopted as the chiplet interconnect scheme of OCP. Farjadrad's work not only led to the adoption of BoW at OCP, but also helped influence UCIe, which is based on the same signaling/clocking schemes and architecture basics and is widely supported in the industry.
An earlier incarnation of the NuLink technology has been mass-produced on a 14 nm process, validating its commercial viability and performance advantages. The most recent version that was taped out at 5 nm delivers a minimum of 2000 Gbps/mm of edge bandwidth on a standard organic package.
View at TechPowerUp Main Site
Eliyan's NuLink PHY and NuGear technologies address the critical need for a commercially viable approach to enabling high performance and cost-effectiveness in the connection of homogeneous and heterogenous architectures on a standard, organic chip substrate. It has proven to achieve similar bandwidth, power efficiency, and latency as die-to-die implementations using advanced packaging technologies, but without the other drawbacks of specialized approaches.
Eliyan's chiplet packaging method is key to realizing the scale of performance and integration required in a broad range of compute intensive applications for data centers, cloud computing, AI and graphics.
The company's founding CEO Ramin Farjadrad is the inventor of the innovative and proven Bunch of Wires (BoW) scheme, which has been adopted by the Open Compute Project (OCP). NuLink technology is backward compatible with Universal Chiplet Interconnect Express (UCIe), a standard developed by Intel and donated to the UCIe Consortium, which includes 80+ leaders in semiconductor, packaging, foundries, cloud services and IP suppliers. Farjadrad's experience includes pioneering work in creating connectivity technologies such as PAM4 SerDes, Multi-Gbps Enterprise Ethernet, and Multi-Gbps Automotive Ethernet that were eventually adopted as IEEE Standards.
Eliyan's Series A round was led by Tracker Capital Management ("Tracker Capital"), which was founded by Stephen A. Feinberg, Co-Founder and Co-Chief Executive Officer of Cerberus Capital Management, L.P. Celesta Capital and other strategic investors including Intel Capital and Micron also participated. As part of the investment from Tracker Capital, made in February 2022, Dr. Shaygan Kheradpir of Cerberus, former Group CIO and a founding member of the Executive Leadership Committee at Verizon, will join the Board of Directors of Eliyan.
Funding supports accelerated validation and commercial readiness
Funding and support from leading industry players enable fast-track design, testing, and implementation ramp-up, culminating with the demonstration of the commercial readiness of Eliyan's best-in-class chiplet interconnect technology in a recent, successful tapeout using TSMC's 5 nm process. The design confirms Eliyan's ability to achieve twice the bandwidth at less than half the power consumption of current interconnect methods and does so using a standard system-in-package (SIP) manufacturing and packaging process. The ability to implement chiplet-based systems in organic packages enables the creation of larger and higher performance solutions at considerably lower power and cost of materials. These factors provide major gains in sustainability.
The company's first silicon is expected in the first quarter of 2023.
"Technology scaling using conventional system on chip (SoC) architectures is hitting the wall, requiring a new approach in how we integrate and manufacture silicon. Our extensive background in developing bleeding-edge technologies in this space led us to focus on a key challenge: interconnect improvements for system-in-package and chip-to-memory architectures as the path to deliver performance scaling," said Eliyan CEO and co-founder, Ramin Farjadrad. "Our approach supports and is compliant with the overall industry move toward chiplet-optimized interconnect protocols, including the UCIe standard as well as High Bandwidth Memory (HBM) protocols. This financial investment by industry leaders and the successful implementation of our design in 5 nm validates our strategy and prepares us for broader commercialization efforts."
Dr. Shaygan Kheradpir of Cerberus commented: "Traditional methods of integrating multi-chip architectures impose challenges that result in high costs, low yield, manufacturing complexity, and size limitations. Eliyan has drawn upon its years of experience to develop a practical scheme that is also backward compatible with existing standards to chiplet interconnect and is optimized for delivering the necessary high bandwidth, low latency, and low power capabilities. We are confident its NuLink technology holds the key to a broader proliferation of chiplets in key market sectors such as hyperscalers, AI processor development, high-performance memory, and advanced graphics chips."
Advanced chiplet interconnect is key to extending Moore's Law
Ulitlizing the manufacturing and cost advantages of chiplets, product developers can continue to scale the performance, power efficiency and size required by high performance computing applications. Industry forecasters estimate the chiplet sector of the semiconductor market will be $50B, with high-bandwidth memory (HBM) applications representing an additional $8B market growing at 50% CAGR.
Eliyan's innovative approach to connecting multi-die chip architectures is achieved without the need for complex and advanced packaging solutions such as silicon interposers. This is essential to cost-effectively leveraging the potential of the fast-growing chiplet-based architectures that experts agree are the pathway to extend Moore's Law.
A track record of interconnect innovation to enable the chiplet ecosystem
Eliyan's BoW approach was specifically developed to address the need for highly efficient die-to-die (D2D) PHYs to connect different functions in one package.
Its NuLink technology, which is a superset of BoW and UCIe, is an innovative PHY technology that uses patented implementation techniques to provide major power-performance differentiation for die-to-die (D2D) connectivity over any packaging substrate, reducing complexity and lowering overall development time and costs. It eliminates the need for advanced packaging solutions, such as silicon interposers that limit overall system-in-package size that ultimately limits performance, results in low wafer test coverage that ultimately impacts yield, increases total cost of ownership, and extends overall manufacturing cycle time.
The company's patented NuGear is an optimized technology for 2.5/3D implementations that enables practical mix and match of chiplets with different die-to-die interfaces in in different processes (DRAM, SOI, etc.).
The technology has been under development by Farjadrad and his team since 2017. In 2018, Farjadrad proposed BoW as a superior chiplet interconnect architecture to OCP. Given the significantly improved performance and features that BoW offered over existing methods, it received strong support and later was adopted as the chiplet interconnect scheme of OCP. Farjadrad's work not only led to the adoption of BoW at OCP, but also helped influence UCIe, which is based on the same signaling/clocking schemes and architecture basics and is widely supported in the industry.
An earlier incarnation of the NuLink technology has been mass-produced on a 14 nm process, validating its commercial viability and performance advantages. The most recent version that was taped out at 5 nm delivers a minimum of 2000 Gbps/mm of edge bandwidth on a standard organic package.
View at TechPowerUp Main Site
