Samsung Electronics Develops Industry's First 12nm-Class DDR5 DRAM

[btarunr]

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, today announced the development of its 16-gigabit (Gb) DDR5 DRAM built using the industry's first 12-nanometer (nm)-class process technology, as well as the completion of product evaluation for compatibility with AMD. "Our 12 nm-range DRAM will be a key enabler in driving market-wide adoption of DDR5 DRAM," said Jooyoung Lee, Executive Vice President of DRAM Product & Technology at Samsung Electronics. "With exceptional performance and power efficiency, we expect our new DRAM to serve as the foundation for more sustainable operations in areas such as next-generation computing, data centers and AI-driven systems."

"Innovation often requires close collaboration with industry partners to push the bounds of technology," said Joe Macri, Senior VP, Corporate Fellow and Client, Compute and Graphics CTO at AMD. "We are thrilled to once again collaborate with Samsung, particularly on introducing DDR5 memory products that are optimized and validated on "Zen" platforms."



This technological leap was made possible through the use of a new high-κ material that increases cell capacitance, and proprietary design technology that improves critical circuit characteristics. Combined with advanced, multi-layer extreme ultraviolet (EUV) lithography, the new DRAM features the industry's highest die density, which enables a 20 percent gain in wafer productivity.

Leveraging the latest DDR5 standard, Samsung's 12 nm-class DRAM will help unlock speeds of up to 7.2 gigabits per second (Gbps). This translates into processing two 30 gigabyte (GB) UHD movies in just one second.

The new DRAM's exceptional speed is matched by greater power efficiency. Consuming up to 23 percent less power than the previous DRAM, the 12 nm-class DRAM will be an ideal solution for global IT companies pursuing more environment-friendly operations.

With mass production set to begin in 2023, Samsung plans to broaden its DRAM lineup built on this cutting-edge 12 nm-class process technology into a wide range of market segments, as it continues to work with industry partners to support the rapid expansion of next-generation computing.

View at TechPowerUp Main Site

 

[JAB Creations]

I know DRAM isn't produced on the latest and greatest manufacturing nodes as it doesn't need to be though it would have been nice to have some contrast between what nodes they are currently using as well as how much less voltage is required for how much of an increase in bandwidth.

 

[TumbleGeorge]

Isn't a 16Gb memory chip too small a capacity by today's standards? What remains to be used for in future products

 

[Wirko]

Isn't a 16Gb memory chip too small a capacity by today's standards? What remains to be used for in future products

Depends on what is a "chip". I prefer to avoid this term because it can mean either "package" or "die".

But in this case, it's about a new die. Four or eight of those get stacked on each package.

I know DRAM isn't produced on the latest and greatest manufacturing nodes as it doesn't need to be though it would have been nice to have some contrast between what nodes they are currently using as well as how much less voltage is required for how much of an increase in bandwidth.

I'm wondering ... is 12 less than 1α? Less than 1β?

But anyway, those are the latest and greatest nodes, made using EUV. It's just that the capacitors can't be shrunk any further, just the transistors can be, so the total benefit is small.

 

[Bloax]

Ah, there's the elusive EUV DRAM at last.