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Qualcomm has been working on its Snapdragon SoCs for quite some time now, with massive success in the mobile phone space. However, the company's processors needed to be up to the task regarding laptops. For a user to not look at x86 offerings, the only remaining performant alternatives are Apple's M processors. In 2021 Qualcomm purchased the Nuvia team that was developing massively efficient and high-performance IP for laptops, similar to Apple M processors. Today, according to the insights from Kuba Wojciechowski (@Za_Raczke) on Twitter, we have some potential information about the upcoming Nuvia-powered SoC codenamed Hamoa.
According to the Twitter thread, Qualcomm's Hamoa processors are part of the Snapdragon 8xc Gen 4 compute platform and feature up to eight high-performance P-cores and four low-power E-cores, all based on Nuvia's IP. Allegedly the P-cores are being tested at 3.4 GHz, while the E-cores are tested at 2.5 GHz. The SoC splits CPU cores into blocks, each being a four-core group with 12 MB of shared L2 cache. There is also an 8 MB L3 cache structure; it needs to be clarified whether it is per core block or for the entire SoC. The chip employs 12 MB of system-level cache, with 4 MB of memory for graphics-related tasks handled by iGPU. The iGPU of choice is Adreno 740, with all modern APIs supported. Discrete graphics solutions are supported by the top-end SKUs, which allow eight PCIe 4.0 lanes to be directed toward dGPU, along with an additional four PCIe 4.0 lanes for NVMe SSD. For RAM, the chip uses up to 64 GBs of LPDDR5X eight-channel memory with up to 4.2 GHz speeds. Chip's media engines are structured to support decoding up to 4K120 and encode up to 4K60 with AV1.
View at TechPowerUp Main Site | Source
According to the Twitter thread, Qualcomm's Hamoa processors are part of the Snapdragon 8xc Gen 4 compute platform and feature up to eight high-performance P-cores and four low-power E-cores, all based on Nuvia's IP. Allegedly the P-cores are being tested at 3.4 GHz, while the E-cores are tested at 2.5 GHz. The SoC splits CPU cores into blocks, each being a four-core group with 12 MB of shared L2 cache. There is also an 8 MB L3 cache structure; it needs to be clarified whether it is per core block or for the entire SoC. The chip employs 12 MB of system-level cache, with 4 MB of memory for graphics-related tasks handled by iGPU. The iGPU of choice is Adreno 740, with all modern APIs supported. Discrete graphics solutions are supported by the top-end SKUs, which allow eight PCIe 4.0 lanes to be directed toward dGPU, along with an additional four PCIe 4.0 lanes for NVMe SSD. For RAM, the chip uses up to 64 GBs of LPDDR5X eight-channel memory with up to 4.2 GHz speeds. Chip's media engines are structured to support decoding up to 4K120 and encode up to 4K60 with AV1.
View at TechPowerUp Main Site | Source
