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Winbond Joins UCIe Consortium to Support High-performance Chiplet Interface Standardisation

TheLostSwede

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Winbond has joined the UCIe (Universal Chiplet Interconnect Express) Consortium, the industry Consortium dedicated to advancing UCIe technology. This open industry standard defines interconnect between chiplets within a package, enabling an open chiplet ecosystem and facilitating the development of advanced 2.5D/3D devices.

A leader in high-performance memory ICs, Winbond is an established supplier of known good die (KGD) needed to assure end-of-line yield in 2.5D/3D assembly. 2.5D/3D multichip devices are needed to realize the exponential improvements in performance, power efficiency, and miniaturization, demanded by the explosion of technologies such as 5G, Automotive, and Artificial Intelligence (AI).




By joining the UCIe Consortium, Winbond supports interconnect standardization that simplifies system-on-chip (SoC) design and eases 2.5D/3D back-end-of-line (BEOL) assembly. The UCIe 1.0 specification provides a complete standardized die-to-die interconnect with a high-bandwidth memory interface, facilitating SoC-to-memory interconnection for low latency, low power, and high performance. Ultimately, standardization will power market growth in advanced multichip engines by accelerating the introduction of higher-performing products that deliver increased value for device makers and end users.

Winbond's 3D CUBE as a Service (3DCaaS) platform gives customers an one-stop shopping service. It includes 3D TSV DRAM (aka CUBE) KGD memory dies and 2.5D/3D BEOL with CoW/WoW optimized for multichip devices, in addition to the consulting service. That is to say; customers can have more completed and comprehensive support from CUBE and with extra value like Silicon-Cap and interposer. Winbond has been committed to providing the best product solution, and by joining the UCIe Consortium is positioned deliver standardized 3D DRAM and 2.5D/3D BEOL services to customers.

"The UCIe specification will enable 2.5D/3D chip technology to realize its full potential in AI applications from the cloud to the edge," said Hsiang-Yun Fan, DRAM Vice President of Winbond. "This technology has a major role in continuing to raise performance as well as ensuring the affordability of cutting-edge digital services."

"We're excited to welcome Winbond to the UCIe Consortium," said Dr Debendra Das Sharma, Chairman UCIe Consortium. "As a global supplier of performance memory solutions with expertise in 3D DRAM, we look forward to their contributions to further developing the UCIe chiplet ecosystem."

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D TSV DRAM (aka CUBE) KGD memory dies and 2.5D/3D BEOL with CoW/WoW
1676487732967.png
 
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On a more serious note, I never heard of Winbond. What exactly do they do, in layman's terms?
A leader in high-performance memory ICs, Winbond is an established supplier of known good die
This makes it sound like they are in the business of taking memory dice from major manufacturers and making packages out of them (to install on the PCB).

I would be curious to see how UCIe 1.0 compares to Ryzen Infinity Fabric, in terms of bandwidth and latency.
 

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On a more serious note, I never heard of Winbond. What exactly do they do, in layman's terms?


Most notably, they make bios chips and other flash ICs. I can 100% guarantee you; that you use their products. Even right now.
 
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Most notably, they make bios chips and other flash ICs. I can 100% guarantee you; that you use their products. Even right now.
Various multi I/O interface chips too. It seems to me that older motherboards couldn't exist without a Winbond centipede on them.

I would be curious to see how UCIe 1.0 compares to Ryzen Infinity Fabric, in terms of bandwidth and latency.
I'm not sure if UCIe defines any communication protocols at all. As I understand it, it's lower level, so it defines the physical and electrical characteristics of wire links intended to carry signals and power across dies, substrates, RDLs, bridges, stacks, and all that modern magic.
 

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I'm not sure if UCIe defines any communication protocols at all. As I understand it, it's lower level, so it defines the physical and electrical characteristics of wire links intended to carry signals and power across dies, substrates, RDLs, bridges, stacks, and all that modern magic.
Based on PCIe, which I am fairly family with, and CXL, which I have no clue about.
 
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Various multi I/O interface chips too. It seems to me that older motherboards couldn't exist without a Winbond centipede on them.

Nothing has changed. Motherboards still cannot exist without LPC interface/Super I/O really. It just has become more crowded. ITE solutions has become more common these days. But Windbond flash is a name everyone should remember for sure.
 
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