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The 43rd edition of the Symposium on VLSI Technology & Circuits, held annually in Kyoto Japan, is charting the way forward for the devices of the future. Held between June 11-16, 2023, this year's symposium will see structured presentations, Q&A, and discussions on some of the biggest technological developments in the logic chip world. The lead (plenary) sessions drop a major hint on the way the wind is blowing. Leadning from the front is an address by Suraya Bhattacharya, Director, System-in-Package, A*STAR, IME, on "Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling."
Companies such as AMD and Intel read the tea-leaves, that Moore's Law is buckling, and it's no longer economically feasible to build large monolithic processors at the kind of prices they commanded a decade ago. This has caused companies to ration their allocation of the latest foundry node to only the specific components of their chip design that benefit the most from the latest node, and identify components that don't benefit as much, and disintegrate them into separate dies build on older foundry nodes, which are then connected through innovative packaging technologies.
The next session is by Siva Sivaram, President, Western Digital, on the scaling limits of 3D NAND flash memory, titled "Searching for Nonlinearity: Scaling Limits in NAND Flash," where he advocates in favor of innovations in the wafer bonding technology to de-couple the memory array from logic circuits, so the NAND flash chip layer count is more purpose-built to the application, and there's a linear cost reduction compared to the current trend, where NAND flash chip designers achieve density increases by "incessantly" increasing 3D NAND flash layers and ending up with sub-linear cost reductions with each generation.
Partha Ranganathan, Vice President, Technical Fellow, Google, is slated to talk on the future of VLSI in six words: "AI-Driven, Software-Defined, and Uncomfortably Exciting." Ranganathan talks about how to rethink hardware design in the future, with a greater emphasis on fuxed-function accelerators, and software-defined systems design. Hiroyuki Mizuno, Distinguished Researcher at Hitachi, takes a top-down approach toward understanding how quantum computing is rapidly moving from hype to that of a "game-changer"
The weeklong event will also see focus sessions on "BEOL/Backside Power Distribution Network (BSPDN)" and "Future Memory Directions," and two full-day short-courses: "Advanced CMOS Technologies for 1 nm & Beyond" and "Future Directions in High-Speed Wireline and Optical IO." TechPowerUp will cover interesting and relevant topics from the symposium.
View at TechPowerUp Main Site
Companies such as AMD and Intel read the tea-leaves, that Moore's Law is buckling, and it's no longer economically feasible to build large monolithic processors at the kind of prices they commanded a decade ago. This has caused companies to ration their allocation of the latest foundry node to only the specific components of their chip design that benefit the most from the latest node, and identify components that don't benefit as much, and disintegrate them into separate dies build on older foundry nodes, which are then connected through innovative packaging technologies.
The next session is by Siva Sivaram, President, Western Digital, on the scaling limits of 3D NAND flash memory, titled "Searching for Nonlinearity: Scaling Limits in NAND Flash," where he advocates in favor of innovations in the wafer bonding technology to de-couple the memory array from logic circuits, so the NAND flash chip layer count is more purpose-built to the application, and there's a linear cost reduction compared to the current trend, where NAND flash chip designers achieve density increases by "incessantly" increasing 3D NAND flash layers and ending up with sub-linear cost reductions with each generation.
Partha Ranganathan, Vice President, Technical Fellow, Google, is slated to talk on the future of VLSI in six words: "AI-Driven, Software-Defined, and Uncomfortably Exciting." Ranganathan talks about how to rethink hardware design in the future, with a greater emphasis on fuxed-function accelerators, and software-defined systems design. Hiroyuki Mizuno, Distinguished Researcher at Hitachi, takes a top-down approach toward understanding how quantum computing is rapidly moving from hype to that of a "game-changer"
The weeklong event will also see focus sessions on "BEOL/Backside Power Distribution Network (BSPDN)" and "Future Memory Directions," and two full-day short-courses: "Advanced CMOS Technologies for 1 nm & Beyond" and "Future Directions in High-Speed Wireline and Optical IO." TechPowerUp will cover interesting and relevant topics from the symposium.
View at TechPowerUp Main Site
