AMD EPYC 8004 Data Center "Siena" CPUs Certified for General SATA and PCI Support

[T0@st]

Keen-eyed hardware tipster momomo_us this week spotted that an upcoming AMD data center "Siena Dense" CPU has received verification, in the general sense, for SATA and PCI support - courtesy of the Serial ATA International Organization (SATA-IO). The information dump was uploaded to SATA-IO's online database on April 6 of this year - under the heading: "AMD EPYC 8004 Series Processors." As covered by TPU mid-way through this month the family of enterprise-grade processors, bearing codename Siena, is expected to be an entry-level alternative to the EPYC Genoa-X range, set for launch later in 2023.

The EPYC Siena series is reported to arrive with a new socket type - SP6 (LGA 4844) - which is said to be similar in size to the older Socket SP3. The upcoming large "Genoa-X" and "Bergamo" processors will sit in the already existing Socket SP5 (LGA 6096) - 2022's EPYC Genoa lineup makes use of it already. AMD has not made its SP6 socket official to the public, but industry figures have been informed that it can run up to 64 "Zen 4" cores. This new standard has been designed with more power efficient tasks in mind - targeting intelligent edge and telecommunication sectors. The smaller SP6 socket will play host to CPUs optimized for as low as 70 W operation, with hungrier variants accommodated up to 225 W. This single platform solution is said to offer 6-channel memory, 96 PCIe Gen 5.0 lanes, 48 lanes for CXL V1.1+, and 8 PCIe Gen 3.0 lanes.



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[psyclist]

Make HEDT Great Again!

 

[LabRat 891]

Please edit title to PCIe 5.0.
The search algorithms/spiders and AI scraping tools will think EPYC has PCI (32-bit) support. (BTW, This happens all the time when I'm searching for components and adapters.)

PCI without any other moniker/suffix typically refers to 32-bit PCI (which, is still used in industrial automation, etc.).
The exception is on the software aide, where PCIe and PCI(-X) are 'software intercompatible'.

Since the article is about hardware, the as-is title implies Siena will have an on-board PCI controller
-companies have been using PCI<->PCIe bridges for that application since Ivy Bridge.
I highly doubt 2023-2024 Intel/AMD SoCs have a 32-bit parallel bus controller in-built.

 

[T0@st]

Please edit title to PCIe 5.0.

Done.

 

[mechtech]

"CPU has received verification for SATA and PCIe 5.0 support"

Seeing this now is about the same as ATA133...............

'SATA was announced in 2000'
'The full 3.0 standard was released on May 27, 2009 - SATA 6 Gbit/s'
Latest rev - Sata rev 3.5 July 2020 misc features - no speed increase.

Be nice if they had 1200 Gbit/s or 2400 Gbit/s

 

[T0@st]

Done.

And reversed.

 

[Patriot]

Make HEDT Great Again!

While this socket could be used for HEDT, This platform is aimed at telecom and is 6 channel DDR5, 32c Zen4, 64c Zen4c 96 lanes gen5, 48 lanes for CXL V1.1+, and 8 PCIe Gen 3.0 lanes.
Allegedly lol.

 

[Wirko]

Please edit title to PCIe 5.0.
The search algorithms/spiders and AI scraping tools will think EPYC has PCI (32-bit) support. (BTW, This happens all the time when I'm searching for components and adapters.)

PCI without any other moniker/suffix typically refers to 32-bit PCI (which, is still used in industrial automation, etc.).
The exception is on the software aide, where PCIe and PCI(-X) are 'software intercompatible'.

Since the article is about hardware, the as-is title implies Siena will have an on-board PCI controller
-companies have been using PCI<->PCIe bridges for that application since Ivy Bridge.
I highly doubt 2023-2024 Intel/AMD SoCs have a 32-bit parallel bus controller in-built.

PCI without 'e' could also refer to PCI-SIG, the body that's responsible for PCI, PCI-X and PCIe standards and also certification/verification. But PCI-SIG isn't mentioned here in the news, nor in the twitter source. Just SATA-IO is.