TSMC N3 Nodes Show SRAM Scaling is Hitting the Wall

[Chrispy_]

This is why AMD pushed cache+memory for Navi 31 to older process node chiplets - because the cache and memory controller scaling with new process nodes has been up against diminishing returns for several years. The fact that TSMC are admitting almost non-existent cache scaling isn't news, it's been godawful for the last half-dozen node shrinks.

IMO the first-gen GPU chiplet design barely justified the effort, but it ought to improve with subsequent generations.

 

[user556]

SRAM dimensions won't be a special case component. Publishing SRAM density is an indicative metric of all surface structures on the die. Scaling has been losing ground on node numbers for years.

Yes, optical resolution is a huge hurdle that has been tweaked to the extreme. FinFET was introduced to exchange horizontal space for vertical. GAA takes that another step.

What do you mean, nothing? 1 MB of L2 is about one third the size of a slice of L3 (= 4 MB next to each core).

Also, L1 in particular, will be multi-ported. These can easily need 10x the real-estate per cell.

 

[TheinsanegamerN]

This is why AMD pushed cache+memory for Navi 31 to older process node chiplets - because the cache and memory controller scaling with new process nodes has been up against diminishing returns for several years. The fact that TSMC are admitting almost non-existent cache scaling isn't news, it's been godawful for the last half-dozen node shrinks.

IMO the first-gen GPU chiplet design barely justified the effort, but it ought to improve with subsequent generations.

*looks at 529mm2 7900xtx*

*looks at 379m2 geforce 4080*

Yeah I think its a little early to call the chiplet GPU "justified".

 

[thegnome]

*looks at 529mm2 7900xtx*

*looks at 379m2 geforce 4080*

Yeah I think its a little early to call the chiplet GPU "justified".

Yeah, justified as a first gen product. The problem isn't too much the tech itself most likely, just that AMD's gpu designs aren't as good as Nvidia's. They've always been behind in efficiency and performance while using similar nodes. Zen's chiplet approach also took years before it got actually quite good.

 

[Wirko]

*looks at 529mm2 7900xtx*

*looks at 379m2 geforce 4080*

Yeah I think its a little early to call the chiplet GPU "justified".

Agreed but don't judge by the millimeters, and of those 529, only 304 are of the more expensive kind. Besides, AMD probably can get 6 nm silicon in less restricted quantities than 5 nm silicon.

 

[AnotherReader]

Yeah, justified as a first gen product. The problem isn't too much the tech itself most likely, just that AMD's gpu designs aren't as good as Nvidia's. They've always been behind in efficiency and performance while using similar nodes. Zen's chiplet approach also took years before it got actually quite good.

You're right about the tech not being at fault for RDNA3's lackluster showing. Funnily enough, there was a time when AMD led in both performance per watt and performance per square mm. Maxwell was the start of Nvidia's dominance; since then, AMD hasn't been able to come close.

 

[THU31]

there is no problem with small size of caches, but problem with unoptimized software.
For well optimized software, few megabytes of cache is sufficient

But then how will Jensen cut the memory controllers for the 50 series if he can't increase the cache size? He might still have to put a 128-bit bus on a $500 card. He might lose some sleep over that.