AMD "Strix Point" Zen 5 Monolithic Silicon has a 12-core CPU?

[btarunr]

It looks like the monolithic silicon that succeeds "Phoenix," codenamed "Strix Point," will finally introduce an increase in CPU core counts for the thin-and-light and ultraportable mobile platforms. "Strix Point" is codename for the next-generation APU die being developed at AMD, which, according to a leaked MilkyWay@Home benchmark result, comes with a 12-core/24-thread CPU.

The silicon is identified by MilkyWay@Home with the OPN "AMD Eng Sample: 100-000000994-03_N," and CPU identification string "AuthenticAMD Family 26 Model 32 Stepping 0 -> B20F00." The "Strix Point" CPU could be the second time AMD has increased CPU core-counts per CCX. From "Zen 3" onward, the company increased the cores per CCX from 4 to 8, allowing a single "Zen 3" CCX on the "Cezanne" monolithic silicon to come with 8 cores. It's highly likely that with "Zen 5," the company is increasing the cores/CCX to 12, and that "Strix Point" has one of these CCXs.



"Strix Point" processors will be branded under the Ryzen 8000 series. Besides the 12-core Zen 5 CPU, it is expected to feature an updated iGPU based on the RDNA3 Gen 2 graphics architecture, and an upgraded memory interface, with support for higher DDR5 and LPDDR5 memory speeds. It's likely that the AMD Radiance Display Engine finds its way to the silicon, as well as an updated XDNA Ryzen AI accelerator. AMD is expected to debut Zen 5 in 2024, with "Strix Point" squaring off against Intel's Core "Meteor Lake" processors.

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[ZoneDymo]

asus ROG Strix point

 

[Daven]

Are the 16 cores in a Zen 4c chiplet contained within one CCX?

 

[HD64G]

My calculated guess is that all APUs will have only Zen5c cores.

 

[ncrs]

Are the 16 cores in a Zen 4c chiplet contained within one CCX?

No, they are split into two CCX. There is no link between the CCXs in a CCD so they have to go through the InfinityFabric on the IO die in order to talk to each other.
You can read a good analysis of Zen 4c at semianalysis.com (it's half-paywalled, but the free part is still enlightening).

My calculated guess is that all APUs will have only Zen5c cores.

In my opinion, I don't think they can afford to lose the absolute performance of "full" cores. A hybrid 5+5c would make more sense than going all 5c, especially on higher end parts like the HX series.

 

[Chrispy_]

IIRC these aren't likely to be 12 full "P-cores" to use Intel's existing nomenclature.

AMD have said Zen5 will include models with non heterogenous "big.LITTLE" architecture like Alder Lake introduced for Intel. Strix Point is rumoured to be 4 full Zen5 cores and 8 Zen5c cores. There's not a lot of concrete info on Zen5c yet, but we're expecting a Zen4c variant this generation at some point which should give us a better idea of how Zen5c is likely to look.

Since these monolithic designs are primarily for laptops, the inclusion of more, smaller Zen5c "e-cores" for lower power draw is the obvious guess for a 12-core mobile part. The hefty, higher TDP desktop-replacement and high-end gaming laptops will likely just use the same MCM parts as desktops (e.g, Dragon Range Ryzen 7045-series) which go up to 16 Zen4 cores across two chiplets as usual.

 

[wNotyarD]

IIRC these aren't likely to be 12 full "P-cores" to use Intel's existing nomenclature.

AMD have said Zen5 will include models with non heterogenous "big.LITTLE" architecture like Alder Lake introduced for Intel. Strix Point is rumoured to be 4 full Zen5 cores and 8 Zen5c cores. There's not a lot of concrete info on Zen5c yet, but we're expecting a Zen4c variant this generation at some point which should give us a better idea of how Zen5c is likely to look.

Since these monolithic designs are primarily for laptops, the inclusion of more, smaller Zen5c "e-cores" for lower power draw is the obvious guess for a 12-core mobile part. The hefty, higher TDP desktop-replacement and high-end gaming laptops will likely just use the same MCM parts as desktops (e.g, Dragon Range Ryzen 7045-series) which go up to 16 Zen4 cores across two chiplets as usual.

Should be heterogeneous or non homogeneous, no?

Apart from that, didn't an AMD spokesperson say they have no interest in building a P/E-core a la Intel, or did that only apply to desktop?

 

[qcmadness]

Should be heterogeneous or non homogeneous, no?

Apart from that, didn't an AMD spokesperson say they have no interest in building a P/E-core a la Intel, or did that only apply to desktop?

The difference between Zen 4 and Zen 4c is the clock speed target. By lowering the clock speed target from 5GHz+ to sub 4 GHz, AMD can increase real transistor density dramatically. There is virtually no IPC difference if the L3 cache size is the same.

 

[wNotyarD]

The difference between Zen 4 and Zen 4c is the clock speed target. By lowering the clock speed target from 5GHz+ to sub 4 GHz, AMD can increase real transistor density dramatically. There is virtually no IPC difference if the L3 cache size is the same.

That's the point. Zen 4c has half the L3 cache of Zen 4, that's what makes it smaller. Clock speeds are then to be defined by binning, core count and power target.

 

[Darmok N Jalad]

No, they are split into two CCX. There is no link between the CCXs in a CCD so they have to go through the InfinityFabric on the IO die in order to talk to each other.
You can read a good analysis of Zen 4c at semianalysis.com (it's half-paywalled, but the free part is still enlightening).


In my opinion, I don't think they can afford to lose the absolute performance of "full" cores. A hybrid 5+5c would make more sense than going all 5c, especially on higher end parts like the HX series.

Considering the space saving nature of Z4C, I'd suspect we'd see either 4R+8C or 8R+4C. This is a monolith, so really the possibilities are all over the place. Considering Z4C is a full Ryzen core with less cache, it's quite possible they could do 4R+8C and performance would probably be similar in most cases.

 

[TumbleGeorge]

I didn't see any indication that will have user experience with Zen "c" cores for home desktop PC's soon.

 

[wNotyarD]

I didn't see any indication that will have user experience with Zen "c" cores for home desktop PC's soon.

Zen 4c doesn't make much sense for desktop Ryzen. It is made to cram more cores while reducing L3 cache. And we all know the crown of AMD's desktop line are the X3D SKUs, with their EXTRA cache.
They could however make a case for workstations. Use Zen 4c for TR 7000, Zen 4 for TR Pro 7000 (or the other way around, whichever benefits more from cores than cache).

 

[Count von Schwalbe]

Zen 4c doesn't make much sense for desktop Ryzen. It is made to cram more cores while reducing L3 cache. And we all know the crown of AMD's desktop line are the X3D SKUs, with their EXTRA cache.
They could however make a case for workstations. Use Zen 4c for TR 7000, Zen 4 for TR Pro 7000 (or the other way around, whichever benefits more from cores than cache).

Ryzen 3/Athlon?

Budget (less cache) -> mainstream (cache) -> halo (more cache)

 

[TumbleGeorge]

Actually yes, for office tasks in companies it makes sense. Some super cheap and low power Athlons, with 4 "c" cores and 8 threads and very light integrated graphics. To replace obsolete Athlon 3000G.

 

[wNotyarD]

Ryzen 3/Athlon?

Budget (less cache) -> mainstream (cache) -> halo (more cache)

Actually, for an Athlon it makes a lot of sense. If memory doesn't fail me K10 Phenoms and Athlons were separated similarly.

 

[Chrispy_]

So the c-cores are cache-starved and lower-clocked, but otherwise full cores?

I'm not sure it'll matter too much either way, the end result is still going to be worse performance unless the OS scheduler puts the right processes on the right cores, so we're still in the situation of relying on the software to deal with the non-homogenous cores (yes, I did mean non-homogenous earlier)

 

[wNotyarD]

So the c-cores are cache-starved and lower-clocked, but otherwise full cores?

I'm not sure it'll matter too much either way, the end result is still going to be worse performance unless the OS scheduler puts the right processes on the right cores, so we're still in the situation of relying on the software to deal with the non-homogenous cores (yes, I did mean non-homogenous earlier)

Cache starved, yes. Lower clocked, not necessarily.
For a core-crammed Bergamo Epyc that's for sure. But as confabulated with @Count von Schwalbe an Athlon (2C/4T or 4C/4T) or a Ryzen 3 (4C/8T or 6C/6T) don't need to have lower clocks, unless they are willingly targeting lower power targets or are badly binned (or not wanting to cannibalize higher SKUs).

Then again, we do have the Cezanne R5 5500X, which has half the L3 cache of the Vermeer brethren.

 

[AnotherReader]

That's the point. Zen 4c has half the L3 cache of Zen 4, that's what makes it smaller. Clock speeds are then to be defined by binning, core count and power target.

No, it isn't just the cache. Each Zen 4c core sans the L2 is nearly half the size of a Zen 4 core. The Zen 4c CCD has more cache than a Zen 4 CCD (16 MB L2 + 32 MB L3) than a regular Zen 4 CCD and it packs twice the cores. Despite that, it's less than 10% larger than the Zen 4 CCD: 72.7 vs 66.3 mm^2. @ncrs linked to an analysis by SemiAnalysis that goes over all this in considerable detail.

 

[wNotyarD]

No, it isn't just the cache. Each Zen 4c core sans the L2 is nearly half the size of a Zen 4 core. The Zen 4c CCD has more cache than a Zen 4 CCD (16 MB L2 + 32 MB L3) than a regular Zen 4 CCD and it packs twice the cores. Despite that, it's less than 10% larger than the Zen 4 CCD: 72.7 vs 66.3 mm^2. @ncrs linked to an analysis by SemiAnalysis that goes over all this in considerable detail.

Nice article, didn't read it first. Didn't know AMD managed to somehow make the logic more compact alongside the L3 cut to make it smaller, so I stand corrected. If this impacts in clock limitations for lower core counts in more lenient packages (let's say a 6-core Ryzen, instead of a 128-core Epyc) it remains to be seen.

But I stand my point for the core/cache equation.
A Z4c CCD has more cache than a Z4 due to being 2 CCX per CCD vs 1, alright. They both have 8 cores/CCX, and while L1 and L2 are the same for each Z4 and Z4c core, shared L3 is halved per Z4c CCX but it has two of them for each CCD so it evens (although it incurs a latency penalty, like Zen 2 and older).
But then we wouldn't be comparing them at the same core count. If we were hypothetically to get both Z4 and Z4c to the exact same core count, Z4c by design has less shared L3 while having the same L1 and L2, CCX's and CCD's notwithstanding.

 

[AnotherReader]

Nice article, didn't read it first. Didn't know AMD managed to somehow make the logic more compact alongside the L3 cut to make it smaller, so I stand corrected. If this impacts in clock limitations for lower core counts in more lenient packages (let's say a 6-core Ryzen, instead of a 128-core Epyc) it remains to be seen.

But I stand my point for the core/cache equation.
A Z4c CCD has more cache than a Z4 due to being 2 CCX per CCD vs 1, alright. They both have 8 cores/CCX, and while L1 and L2 are the same for each Z4 and Z4c core, shared L3 is halved per Z4c CCX but it has two of them for each CCD so it evens (although it incurs a latency penalty, like Zen 2 and older).
But then we wouldn't be comparing them at the same core count. If we were hypothetically to get both Z4 and Z4c to the exact same core count, Z4c by design has less shared L3 while having the same L1 and L2, CCX's and CCD's notwithstanding.

I agree that decreasing the L3 size is an important contributor to the small size of the Zen 4c CCD. However, they did a lot of work all around the core to increase density. As far as clock speeds in low core count SKUs are concerned, I expect this to clock significantly less than Zen 4. Denser designs typically trade off clock speed for area.

 

[wNotyarD]

I agree that decreasing the L3 size is an important contributor to the small size of the Zen 4c CCD. However, they did a lot of work all around the core to increase density. As far as clock speeds in low core count SKUs are concerned, I expect this to clock significantly less than Zen 4. Denser designs typically trade off clock speed for area.

Which would pose a bit of problem for marketing a possible Zen 4c Ryzen 3 (it's still Ryzen so it should be fast, right?). For an Athlon, though? It would be amazing for any office pc.

Off-topic: it makes me sad everytime I see Athlon relegated to the boring, slower, lesser CPU. Oh, the memories...

 

[Count von Schwalbe]

If this impacts in clock limitations for lower core counts in more lenient packages (let's say a 6-core Ryzen, instead of a 128-core Epyc) it remains to be seen.

When not power-limited, yes clocks will be less.

It should clock higher when the W/core is low, such as in high core count CPUs and laptops.

Off-topic: it makes me sad everytime I see Athlon relegated to the boring, slower, lesser CPU. Oh, the memories...

And Pentium/Celeron?

 

[AnotherReader]

Which would pose a bit of problem for marketing a possible Zen 4c Ryzen 3 (it's still Ryzen so it should be fast, right?). For an Athlon, though? It would be amazing for any office pc.

Off-topic: it makes me sad everytime I see Athlon relegated to the boring, slower, lesser CPU. Oh, the memories...

It would be fine for augmenting the multithreaded prowess of higher core count SKUs, but would be unsuited to core counts lower than 8.

I agree: the Athlon was the original "big damn hero" for AMD and the rest of the PC world. I also have similar thoughts when I see the Pentium name used for low performance SKUs. They should have kept Celeron for that use, and retired the Pentium brand.

 

[wNotyarD]

And Pentium/Celeron?

I agree: the Athlon was the original "big damn hero" for AMD and the rest of the PC world. I also have similar thoughts when I see the Pentium name used for low performance SKUs. They should have kept Celeron for that use, and retired the Pentium brand.

As there's no Athlon newer than the Picasso 3150GE, better case scenario it's only dormant unlike Pentiums and Celerons (not that I liked the latter - and Semprons - much) which are officially RIP.

 

[Count von Schwalbe]

It would be fine for augmenting the multithreaded prowess of higher core count SKUs, but would be unsuited to core counts lower than 8.

Reduced prices as the die area is much much lower. 4-core CPUs don't make any sense as TSMC N5 is pretty mature, so there is not much reason to disable two more working cores and reduce profit margins.

Now a 6-core Zen 4c CCD would make sense, and disabled units for Athlons.