A question for all the silicon experts out there
@TheLostSwede and others.
If you can make chiplet and slap all that stuff on an interposer??................would it be possible to take say 2 small cheaper chips like an RX6600 and 'glue' them together?? Would it work and be cheaper than a single RX6800 chip??
Most likely not right now, due to the assembly fabs that does that kind of stuff being run at 110% capacity.
In theory, it could be, assuming the chip to chip latency would be low enough, which apparently is one of the big hurdles today for something like that when it comes to GPUs, from my understanding of it.
I guess this company is hoping to win that kind of business in the future.
Somewhat out of the blue, Silicon Box has announced the opening of its US$2 billion semiconductor assembly plant in Singapore. The "startup" is founded by several of Marvell's founders, suggesting the company has the right pedigree to compete in what is sure to be a very competitive market over...
www.techpowerup.com
In my opinion it would be cheaper.
They would have better yields and lower development costs, as they would have to develop only one "small" chip that would be scaled from low-end to high-end just by putting together 1, 2, 3, 4 of these base GPU/GDC, as already happens in ryzen and EPYC. The question is, If AMD could pull the magic out of the hat and make it work flawlessly (for gaming)...
Long term yes, but not today, due to the the points above. But it does really seem to be the way a lof of companies are heading, as it's simply not viable to make massive chips with low yields.
A large part of it will depends on AMD's (or whoever's) partners as well, as the chip packaging companies need to be able to deliver flawless chips on their end as well, which I believe isn't always the case today, as this is still relatively new technology at the level it's being done these days and even more so as it gets more complex.
We also seem to need better chiplet interconnects that can handles every growing bandwidths, without adding latency or some other issues.
We'll most like end up with a combination of this and 3D stacking, as long as the thermals can be controlled when 3D stacking is used.
I think the latency between chiplets would be too high. If the "magic" was that easy, they would have already done it with RDNA 3, imo.
It's a step by step process, this was clearly a step to try a lot of things, that didn't quite pan out as planned, so back to the drawing board.
It took AMD a few generations with Ryzen as well to get it to where it is today and what it pressumably will be in the near future.
It's by no means magic and as pointed out above, a lot of it will depend on their partners to deliver packaging solutions that can handle the negatives from doing this well enough, the key one as you point out being latency.
Very well said! People tend to forget that Ryzen didn't take the chiplet route because it's better for us - far from it. It's cheaper to make, that's it. If anything, we're losing on it with the complications in cooling the offset chips, and the higher idle power consumption.
If it's so bad, why is Intel heading in the same direction as AMD?
