I'm also hoping for more than a die shrink, but the jump from N6 to N5 isn't as great as you think. Let's take a look at four AMD GPUs to estimate what a N6 to N5 transition could do. The four GPUs are:
- RX 7600: N6, 32 CUs, 128 bit DRAM bus, 32 MB LLC, 204 mm^2 die size
- RX 6600 XT: N7, 32 CUs, 128 bit DRAM bus, 32 MB LLC, 237 mm^2 die size
- RX 6700 XT: N7, 40 CUs, 192 bit DRAM bus, 96 MB LLC, 335 mm^2 die size
- RX 7800 XT GCD: N5, 60 CUs, 200 mm^2 die size
Estimates for the die area of various blocks in the 6700 XT are: 58.46 mm^2 for the 96 MB LLC, 9.53 mm^2 for the 3 MB L2, 29.09 mm^2 for the 192-bit GDDR6 PHY, and 4.6 mm^2 for 16 PCIe 4 lanes. Extrapolating this to the 6600 XT and the 7600 yields 19.49 mm^2 for the 32 MB LLC, 6.35 mm^2 for the 2 MB L2, 19.39 mm^2 for the 128-bit GDDR6 PHY, and 2.3 mm^2 for 8 PCIe 4 lanes. This leaves 156.5 mm^2 for the 7600 and 189.5 mm^2 for the 6600 XT sans their L2, LLC and off chip IO PHYs. This yields a 21% increase in density going from N7 to N6. Now, it's unlikely to be the process alone; design probably plays a part too. Note that we haven't accounted for the larger media engine of the 7600.
Using the same process to estimate the die area of a 60 CU 6700 XT sans the same blocks gives us 362.66 mm^2 for N7 which is 299.5 mm^2 for N6. We haven't accounted for the larger register file in RDNA3 which would make the scaling better, but this works as a starting point. This suggests that Intel is unlikely to manage anything more than 48 EUs for Battlemage in a die of the same size as the one used for the A770.