Intel Meteor Lake P-cores Show IPC Regression Over Raptor Lake?

[btarunr]

Intel Core Ultra "Meteor Lake" mobile processor may be the the company's most efficient, but isn't a generation ahead of the 13th Gen Core "Raptor Lake" mobile processors in terms of performance. This isn't just because it has an overall lower CPU core count in its H-segment of SKUs, but also because its performance cores (P-cores) actually post a generational reduction in IPC, as David Huang in his blog testing contemporary mobile processors found out, through a series of single-threaded benchmarks. Huang did a SPECint 2017 performance comparison of Intel's Core Ultra 7 155H, and Core i7-13700H "Raptor Lake," with AMD Ryzen 7 7840HS, 7840H "Phoenix, Zen 4," and Apple M3 Pro and M2 Pro.

In his testing, the 155H, an H-segment processor, was found roughly matching the "Zen 4" based 7840U and 7840HS; while the Core i7-13700H was ahead of the three. Apple's M2 Pro and M3 Pro are a league ahead of all the other chips in terms of IPC. To determine IPC, Huang tested all processors with only one core, and their default clock speeds, and divided SPECint 2017 scores upon average clock speed of the loaded core logged during the course of the benchmark. Its worth noting here that the i7-13000H notebook was using dual-channel (4 sub-channel) DDR5 memory, while the Core Ultra 7 155H notebook was using LPDDR5, however Huang remarks that this shouldn't affect his conclusion that there has been an IPC regression between "Raptor Lake" and "Meteor Lake."



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[pavle]

We shall see what further testing reveals, but looks like at intel they're still actively digging their grave...

 

[P4-630]

Well, as it looks right now, I will install a Apple M3 Pro chip in my Z690 board next year....

Might need some light modding though.. But I'll be fine after that...

 

[atomek]

Maybe Intel should start making motherboard chipsets for Apple Silicon? They should be capable of doing this.

 

[Chaitanya]

We shall see what further testing reveals, but looks like at intel they're still actively digging their grave...

But hey atleast their CEO is effective at begging for funds from government at taxpayers expense.

 

[LemmingOverlord]

Maybe Intel should start making motherboard chipsets for Apple Silicon? They should be capable of doing this.

I hope you're being genuinely sarcastic because it doesn't work that way.

 

[john_]

Well, it's their first 7nm right? So they might need to start a little more carefully with this new process, meaning turboing in a much safer zone.
Or maybe they are going one step back, so they can sell higher IPC with their next series.
Or both.

 

[R0H1T]

Might need some light modding though.. But I'll be fine after that...

You might wanna check your Apple card expiry as well

 

[john_]

Maybe Intel should start making motherboard chipsets for Apple Silicon? They should be capable of doing this.

Chipsets? Apple's chips are SOCs, they don't really need chipsets. So, even if this was a serious idea and Apple wasn't having problems with it, it wouldn't work anyway.

 

[ncrs]

Well, Intel only claimed IPC gains for E-cores in Meteor Lake while P-cores were supposed to increase efficiency

 

[FoulOnWhite]

Isn't meteor lake the first intel multi tile chip? If so maybe they need to tweak it, after so long doing it the other way.

 

[ncrs]

Isn't meteor lake the first intel multi tile chip? If so maybe they need to tweak it, after so long doing it the other way.

It's not - Sapphire Rapids (4 tiles) and Ponte Vecchio (63 tiles) utilized it before.
Meteor Lake is the first consumer chip to use them, and also the first consumer product utilizing the Intel 4 process.
IMO the new process has a higher chance of influencing IPC than the fact it uses tiles, but more research is required.

 

[MaMoo]

It's not - Sapphire Rapids (4 tiles) and Ponte Vecchio (63 tiles) utilized it before.
Meteor Lake is the first consumer chip to use them, and also the first consumer product utilizing the Intel 4 process.
IMO the new process has a higher chance of influencing IPC than the fact it uses tiles, but more research is required.

I have a 24 core Sapphire Rapids chip (not sure if this one uses tiling or not) and I am disappointed in its performance. Per core, it was a lot slower than my 12700k desktop.

I did some benching and on some Linpack tests, I was able to get about 500 gigaflops on 24 threads on Sapphire Rapids, whereas I got 333 gigaflops on 8 threads on the 12700k in stock form (e-cores disabled in BIOS).

I plan to do more tests to profile the Sapphire Rapids soon.

 

[ThomasK]

Wasn't Intel's PR material calling their competitor out for "gluing" its chips together (referring to the MCM approach), yet they ended up doing the same with Meteor Lake, but now with alleged lower performance? How ironic.

 

[FoulOnWhite]

Wasn't Intel's PR material calling their competitor out for "gluing" its chips together (referring to the MCM approach), yet they ended up doing the same with Meteor Lake, but now with alleged lower performance? How ironic.

It's not glued, much more sophisticated than that, glued is a prehistoric joke now

 

[ThrashZone]

Hi,
Still glad I opted for 7840hs

 

[phanbuey]

But hey atleast their CEO is effective at begging to funds from government at taxpayers expense.

Have you seen the other stuff our government spends money on?

That's hardly their worst investment.

Plus if Intel Fabs are good then they might be manufacturing for AMD and Apple in the future.

In any case the meteor lake architecture seems pretty weak -- hopefully the arrow lake core is much stronger.

 

[ncrs]

I have a 24 core Sapphire Rapids chip (not sure if this one uses tiling or not) and I am disappointed in its performance. Per core, it was a lot slower than my 12700k desktop.

I did some benching and on some Linpack tests, I was able to get about 500 gigaflops on 24 threads on Sapphire Rapids, whereas I got 333 gigaflops on 8 threads on the 12700k in stock form (e-cores disabled in BIOS).

I plan to do more tests to profile the Sapphire Rapids soon.

It depends on the model - there are six 24-core Sapphire Rapids SKUs. Xeon W-2400 series is monolithic, while Xeon W-3400 and "big" Xeons are tiled.
Server CPUs are usually running at lower frequencies than desktop parts are capable of, especially for 1-core turbo. The highest 1T frequency for 24-core Xeons is 4.0GHz while 12700K goes to 5.0GHz and can be OCd further. Xeon-W can go up to 4.8GHz but their TDP is ~100W higher than equivalent Xeon. This behaviour is not unique to Intel.
While testing you should also consider that by default desktop Intel CPUs are no longer limited in PL2 turbo duration (since Alder Lake), while professional CPUs adhere to their limits. Some mainstream motherboards will also modify power limits by default.

 

[Denver]

There must be some inconsistency in the methodology, two identical CPU models (7840u and 7840HS) at the silicon level, are presenting different IPC.

 

[Squared]

Wasn't Intel's PR material calling their competitor out for "gluing" its chips together (referring to the MCM approach), yet they ended up doing the same with Meteor Lake, but now with alleged lower performance? How ironic.

Intel specifically criticized the memory controller in the first generation Epyc processors, because each chip had its own memory controller, so each had a pool of the main memory and there was a latency penalty for pulling from a different pool. It was almost like 4-socket system but in one package. Second generation Epyc along with all of Ryzen and Meteor Lake all have a fully unified memory controller so they don't have this issue.

 

[Tigerfox]

Wasn't Intel's PR material calling their competitor out for "gluing" its chips together (referring to the MCM approach), yet they ended up doing the same with Meteor Lake, but now with alleged lower performance? How ironic.

AMD did the same with Intel back in the times of Pentium D, because those were just two prescott cores slapped together in one DIE and unable to cummunicate with each other. It was the same for Core 2 Quad AFAIR.

 

[Squared]

There must be some inconsistency in the methodology, two identical CPU models (7840u and 7840HS) at the silicon level, are presenting different IPC.

Yeah I don't see a mention of how this testing method stabilizes clock speeds. IPC testing I've seen in the past locks two different processors with similar max clock speeds at the same clock speed. I hear that IPC actually changes at different clock speeds so it breaks down somewhere, but certainly if you don't use a fixed clock speed, then you won't have an accurate single frequency to divide out to get the IPC.

Also for Alder Lake the OS puts threads on the P cores first, whereas with Meteor Lake the OS starts with the LPE cores. How do we know this benchmark isn't starting on an LPE core and getting moved too late?

And what I've heard is that Redwood Cove is little more than a die shrink of Raptor Cove. So I expect it to have identical IPC and I want stronger evidence than this to stop believing that.

Then again, the memory controller in Meteor Lake is on a different tile. Maybe that hurts performance more than we realized. It ought to hurt Ryzen's chiplets even more but Zen 2 introduced chiplets and I've never seen an IPC comparison between Zen 2 desktop (chiplets) and mobile (monolithic). (And Zen 2 had much higher IPC than Zen 1.)

 

[usiname]

And what I've heard is that Redwood Cove is little more than a die shrink of Raptor Cove. So I expect it to have identical IPC and I want stronger evidence than this to stop believing that.

Even Intel on the release of Meteor Lake showed slides with regression in the single core compared to the 1360P (or 1370P?) which is lower tier than the 13000H with lower or similar clocks so the IPC regression is expected

 

[ncrs]

Intel specifically criticized the memory controller in the first generation Epyc processors, because each chip had its own memory controller, so each had a pool of the main memory and there was a latency penalty for pulling from a different pool. It was almost like 4-socket system but in one package. Second generation Epyc along with all of Ryzen and Meteor Lake all have a fully unified memory controller so they don't have this issue.

But that is exactly what happens on Sapphire Rapids - each tile has a memory controller complex with two channels each

As you said this increases latency, so Intel supports emulating NUMA on those CPUs so that you can split the memory and cores into 2/4 logical regions to avoid the memory latency issues. The OS can then optimize process scheduling to keep the cores and their memory together.
This isn't unique to SPR since previous Xeons, that are monolithic, also allowed this because even though all of the controllers were on the same die they were located at the edges and still had differing latency depending on core location. This issue is present in every multi-core CPU, but its impact is negligible unless you start scaling core counts up.
Every AMD EPYC generation also has a mechanism like that, and even one that goes further and divides the CPU along the physical L3 cache locations. Even EPYCs with IO dies, containing a monolithic memory controllers, can be set to "lock" memory channels to Infinity Fabric links that serve particular CCDs.
Many workloads yield improvements by using those mechanisms, and both vendors publish extensive documentation on how to configure their professional CPUs.

 

[Daven]

Lol! I knew it! Serious MTL p core IPC increase rumors were false. Now if Arrow Lake uses the same p core then Intel will have released less IPC at the end of 2024 than Alder Lake from 2021.