Detailed Intel Arrow Lake-S Platform Specifications Leaked, Confirms Native Thunderbolt 4 Support

[Wirko]

They do. But no-one has implemented it slot wise, as the motherboard makers most likely don't think anyone is going to want to lower the speed of their PCIe 5.0 x4 drives in favour of being able to have an additional drive.
PCIe obviously allows for down to x1 in a x16 slot, so if you want to install some janky M.2 adapters to your M.2 slots to split four lanes into two, go ahead, it will work, at least on AMD.

Epycs, Threadrippers and Xeons are all really good when it comes to PCIe 5.0 lane splitting, with Xeons being a bit inferior. But consumer stuff? Intel has 8+8+4 and AMD has 8+8+4+4 if we count all PCIe 5.0 lanes available in the system. The 5.0 x4 ports don't allow further splitting (I've never seen it documented anywhere) and the 5.0 x8 ports (two halves of the PEG bus) may allow splitting to x4. Neither Intel nor AMD mandate that, so the support depends on the motherboard manufacturers.

And I think bifurcation is becoming/will become more appealing now that we have 5.0. "I don't need the ultimate speed, I need the lanes!" is an opinion I've often seen expressed here at TPU forums. Those who need the lanes actually need the ability to connect many devices, SSDs, graphics cards, network cards, basically to squeeze out workstation-level connectivity from a consumer desktop system.

The splitter you linked to ... it's unclear if it's a passive splitter or it has a PCIe bridge chip onboard. The price difference is huge if we're talking PCIe 5.0 or 4.0.

 

[TheLostSwede]

Epycs, Threadrippers and Xeons are all really good when it comes to PCIe 5.0 lane splitting, with Xeons being a bit inferior. But consumer stuff? Intel has 8+8+4 and AMD has 8+8+4+4 if we count all PCIe 5.0 lanes available in the system. The 5.0 x4 ports don't allow further splitting (I've never seen it documented anywhere) and the 5.0 x8 ports (two halves of the PEG bus) may allow splitting to x4. Neither Intel nor AMD mandate that, so the support depends on the motherboard manufacturers.

And I think bifurcation is becoming/will become more appealing now that we have 5.0. "I don't need the ultimate speed, I need the lanes!" is an opinion I've often seen expressed here at TPU forums. Those who need the lanes actually need the ability to connect many devices, SSDs, graphics cards, network cards, basically to squeeze out workstation-level connectivity from a consumer desktop system.

The splitter you linked to ... it's unclear if it's a passive splitter or it has a PCIe bridge chip onboard. The price difference is huge if we're talking PCIe 5.0 or 4.0.

You need to learn to differentiate between something that is possible and what the motherboard makers implement, the two aren't the same.
Several AMD boards have x2 electrically connected x16 slots for example, so it's very much doable to implement x2 interfaces on AMD and I presume Intel these days.

I also think you've misunderstood how PCIe and bifurcation works. Just because you go from PCIe 5.0 to PCIe 4.0 from a PCIe 5.0 interface, doesn't mean the eight lanes you split off, magically turns into 16 lanes without some kind of bridge chip in the middle. If this is what you want, then PCIe and/or bifurcation isn't going to do it, since neither was designed to do this.

 

[TumbleGeorge]

"3 x GbE"? 3 x rj45?

 

[Tek-Check]

At the very least, the PCIe 5.0 x4 interfaces on the CPUs should support splitting to x2 + x2. Samsung's 990 Evo SSD, if it becomes a reality, is an indication that this is going to happen.

It works. 8500G and 8300G APU will be able to work in x4 slot as x2 device.

The 5.0 x4 ports don't allow further splitting (I've never seen it documented anywhere)

Check new Gigabyte board B650 that supports new Zen4 APUs. Every NVMe slot supports both x4 and x2 connections.

B650 GAMING X AX (rev. 1.5) Specification | Motherboard - GIGABYTE Global

Lasting Quality from GIGABYTE.GIGABYTE Ultra Durable™ motherboards bring together a unique blend of features and technologies that offer users the absolute ...

www.gigabyte.com

And I think bifurcation is becoming/will become more appealing now that we have 5.0. "I don't need the ultimate speed, I need the lanes!" is an opinion I've often seen expressed here at TPU forums. Those who need the lanes actually need the ability to connect many devices, SSDs, graphics cards, network cards, basically to squeeze out workstation-level connectivity from a consumer desktop system.

This is unrealistic expectation. If anyone wants "workstation-like connectivity", they need to buy a workstation system. Simple.
When X670E or Z790 chipsets are creatively implemented on a board, those allow for HEDT-like connectivity.
Top chipset consumer desktop system does not need to offer anything else.
Still want more connectivity? Pay for it.

 

[TheLostSwede]

"3 x GbE"? 3 x rj45?

At the cost of PCIe lanes. Just like it is with current platforms.

 

[Shonk]

Its Fake

The PCH DMI link says DMI 3 x 8

thats weird Z690/Z790 is DMI 4 x 8

 

[TheLostSwede]

Its Fake

The PCH DMI link says DMI 3 x 8

thats weird Z690/Z790 is DMI 4 x 8


View attachment 330772

There are several weird issues, but if this is really for pre-Alpha hardware, I wouldn't be surprised if there were mistakes like this. I've pointed out a few more.

 

[Squared]

What does the snip mean with 8 cores 16. Is it a max 8p core and 16 e core config? 125 watt tdp? what does the +1 mean?

Meteor Lake and Arrow Lake have very similar "tile" plans. Meteor Lake has the CPU memory controller on one tile and the CPU cores on another, which means that two pieces of silicon have to be active for any CPU task. This isn't ideal for idle power consumption, which is problematic especially in laptops. (This is probably why AMD still uses a monolithic die for their laptop APUs.) To address this problem, Meteor Lake has two additional "low power efficiency" CPU cores on the same tile as the memory controller, so that when idling the entire CPU tile can turn off but light CPU work can still be done. Meteor Lake's top model is 6p+8e+2lpe. So this Arrow Lake claim is that it has one low power efficiency core.

 

[persondb]

If this holds any truth, this means that Arrow Lake platform could have better I/O than AM5.

At the average Motherboard they are probably the same though as Intel middle range chipsests (e.g. B-class) tend to only have DMI x4, so it will be 24 PCIe lanes direct from CPU + 4 PCH lanes, which is the same as AM5. The generations of the lanes are also the same with 20 Gen 5(if implemented as that) and 4 Gen 4.

The PCHs might have some variations in what lanes they provide but for peak performance in the end, they can only effectively provide bandwidth in total equal to x4 Gen 4 for both cases so it does not matter that much.

Intel however gets the advantage in I/O if TB4/USB4 are implemented, as since it's native to the CPU, it does not need to use any of the PCIe lanes from the CPU but AM5 does need(and that was one of the reasons why AMD gave an additional x4 lanes over AM4, to facilitate a discrete USB4 controller) a discrete USB4 controller connected to x4 lanes.

And then you have the PCH bandwidth advantage as with with x8 lanes using a H or Z chipset gives more leg for the downstream ports to stretch really. which will make a difference to those who are abusing their PCH connectivity to the max.

For the average person or gamer, it does not matter at all though, since this will really only pop up at super expensive boards that only people with real needs will buy.

 

[Nekajo]

Is Arrow Lake confirmed to be made on the 20A node?

 

[Squared]

Is Arrow Lake confirmed to be made on the 20A node?

That is what Intel has said, but Intel also said that Lunar Lake would succeed it on the 18A node, but now Intel says that Lunar Lake is in production even though 18A isn't scheduled to be in production yet and Intel has said that Arrow Lake and Lunar Lake will both come this year and has described the former as for the "enthusiast" market and the latter for the "mobile" market. But Intel claimed in the past that Arrow Lake would be 20A and more recently claimed that 20A is in production, those claims do line up to suggest that Arrow Lake is on track for release this year on 20A. I believe Intel has said or hinted that only the CPU tile will use the 20A node, similar to Meteor Lake and the Intel 4 node.

(Intel says that Lunar Lake has a different tile configuration from Meteor Lake and Arrow Lake. The rumor mill says that a 4p+4e CPU will be on the same tile as an Xe2 GPU, and that tile will be built on TSMC N3. Maybe Intel is trying to avoid criticism about Lunar Lake being built by TSMC until they have Arrow Lake ready to show off on their own node.)