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Huawei and SMIC Prepare Quadruple Semiconductor Patterning for 5 nm Production

AleksandarK

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According to Bloomberg's latest investigation, Huawei and Semiconductor Manufacturing International Corporation (SMIC) have submitted patents on the self-aligned quadruple patterning (SAQP) pattern etching technique to enable SMIC to achieve 5 nm semiconductor production. The two Chinese giants have been working with the Deep Ultra Violet (DUV) machinery to develop a pattern etching technique allowing SMIC to produce a node compliant with the US exporting rules while maintaining the density improvements from the previously announced 7 nm node. In the 7 nm process, SMIC most likely used self-aligned dual patterning (SADP) with DUV tools, but for the increased density of the 5 nm node, a doubling to SAQP is required. In semiconductor manufacturing, lithography tools take multiple turns to etch the design of the silicon wafer.

Especially with smaller nodes getting ever-increasing density requirements, it is becoming challenging to etch sub-10 nm designs using DUV tools. That is where Extreme Ultra Violet (EUV) tools from ASML come into play. With EUV, the wavelengths of the lithography printers are 14 times smaller than DUV, at only 13.5 nm, compared to 193 nm of ArF immersion DUV systems. This means that without EUV, SMIC has to look into alternatives like SAQP to increase the density of its nodes and, as a result, include more complications and possibly lower yields. As an example, Intel tried to use SAQP in its first 10 nm nodes to reduce reliance on EUV, which resulted in a series of delays and complications, eventually pushing Intel into EUV. While Huawei and SMIC may develop a more efficient solution for SAQP, the use of EUV is imminent as the regular DUV can not keep up with the increasing density of semiconductor nodes. Given that ASML can't ship its EUV machinery to China, Huawei is supposedly developing its own EUV machines, but will likely take a few more years to show.



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As an example, Intel tried to use SAQP in its first 10 nm nodes to reduce reliance on EUV, which resulted in a series of delays and complications, eventually pushing Intel into EUV.
And now Intel rushed to buy the first machine of the latest model from ASML to be sure it wouldn't f...up again.
 
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If I were ASML, I wouldn't have my IP on anything connected to the internet...
 
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Also quadruple the cost and defect rate ?
 
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And now Intel rushed to buy the first machine of the latest model from ASML to be sure it wouldn't f...up again.
DUV with multi-patterning is much cheaper and produces results as good or better than single pass EUV and can work down to 2nm node. Intel has rushed out and purchased 6 first gen EUV machines that won't make any financial sense until 1.4nm. I doubt it takes 4 years to setup and validate the machines.
 
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