Lots of really fascinating info/takes is this thread, thanks all for your contributions (and for helping inform people/make the whole ecosystem better).
I, for one, had forgotten the limits to specs (other than flops) wrt exports to China (which may impact some 'stock' product decisions beyond 4090D, perhaps even how certain chips are designed with that limitation in mind in the future) in ways I haven't personally looked into on a deep-enough level to comment. Thanks for the info/reminder.
That said, GDDR would be volatile memory, correct? I imagine (but am not well-versed on the current definition of I/O bw) this is in relation to external bandwidth (links/protocol) and if anything may perhaps only relate to their (capabilities of) external cache structure? While I don't know the actual bw (or limitations of the link), using it's observational impact on performance I've generally equated AMD's L3 structure to something like adding 3mhz(/gbps) over the bus in relation to core speed (as the cache is likely clocked in relation to core; haven't looked into it). So, for instance, if something like a 7800xt/7900gre were running at 2800mhz core clock, the L3 would be contributing what equates to 268.8Gbps for DRAM bw. Obviously it's faster as the size is smaller, but in terms of perf does appear to shake out if you look at it wrt bw limitations. The same is true of nVIDIA's L2 cache and roughly double at same size (similar to core clock*6mhz over the bus), which nVIDIA all-but-confirmed with one product release not so long ago (something in the 4060/4070 series iirc) to excuse the more narrow bus wrt the competition.
In the case of 4090 (with 72MB L2), for instance, that translates to something like ~2730*4.5*384/8 = ~589.68Gbps, which is indeed oddly close to the number you stated. That's internal though, so I don't know if that was part of that decision-making process of the chip and/or effected by those export rules (or rather the rules were built around them after it was completed and/or released)? Now you've got me curious, but I always had a feeling these 'rules' were constructed as a compromise between the government and nVIDIA as for them to still be able use that chip in China, but for them to be conscious of using restraint moving forward.
I'm sure someone more studied could read those last couple paragraphs and declare me a simpleton, and that's fair-enough! I respect there are people that know much more in the intricate areas of these things (and their definitions/classifications) than I do, have have kept up on it better, and/or have information most don't have. I generally focus on the real-world impact to most users, and where limitations are/how they can be improved. I don't always know the correct specific language/terminology regarding how each area is classified. I'm sure there are people around here that can shed much more light on it than myself. I don't *think* what you are implying would apply, but I absolutely could not state that as a fact as I just don't have the inherent knowledge or haven't done the reseach to declare that as fact.
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