AMD Zen 5 Chiplet Built on 4 nm, "Granite Ridge" First Model Numbers Leaked

[atomsymbol]

Of course, and I would also be selling bullshit. Every new gen is a new iteration of something built upon before. Calling the first Zen a real grounds-up architecture, I think is quite accurate, but even that is built upon decades of experience.

By such logic, the *only* grounds-up x86 architecture was the Intel 4004 CPU (year 1971).

 

[Vayra86]

By such logic, the *only* grounds-up x86 architecture was the Intel 4004 CPU (year 1971).

Well, I would rather say there are many ways to interpret grounds-up, and the one we're reading here is mostly marketing oriented. The changes are not that radical here.

Also, we've seen AMD say 'grounds-up' before and it can mean any range of things between 'half finished' (RDNA!), 'full of holes', 'a truly new thing because we're fucked otherwise', 'a refinement of what we have'.

Anything that is truly 'grounds-up' also represents a major risk. Zen 5 is far from that. They're taking the best bits and add new good bits.

 

[atomsymbol]

Well, I would rather say there are many ways to interpret grounds-up, and the one we're reading here is mostly marketing oriented. The changes are not that radical here.

Well, yes. But on the other hand, almost everything published on TechPowerup is to some extent marketing oriented. I think you should just filter out the marketing stuff when reading TechPowerup - complaining in the forums that the news contain marketing disinformation is counterproductive and a net-loss of your time.

 

[Vayra86]

Well, yes. But on the other hand, almost everything published on TechPowerup is to some extent marketing oriented. I think you should just filter out the marketing stuff when reading TechPowerup - complaining in the forums that the news contain marketing disinformation is counterproductive and a net-loss of your time.

Uh? I'm not complaining, just putting a slide's outings in perspective. Because many people read marketing and take it for granted, even the things often read as 'normal'. If you keep getting told something is truly revolutionary, it probably is, right? Meanwhile, after buying it you see minor improvements in performance and you might think 'hm... theory != reality'.

I also don't consider that a loss of my time. High educational value. Especially if experience is limited.

 

[LabRat 891]

Yeah about as fresh as Core by now, let's not fool each other here. Grounds-up, so they recompiled it. Great Its still a Zen CPU. Grounds-up means exactly nothing, or about as much as nanometer processes now.

Zen 1 was grounds-up. This is another Zen CPU


AI is already a marketing advantage, just not on the consumer side. And it won't likely go there either. I still have enough faith in humanity. We're trying it out now, and the early results are not encouraging. Meanwhile, the real cost of these solutions is slowly becoming impossible to hide for us, and they. Are. Immense.

The cost/benefit scenario just doesn't work here. We couldn't do an autonomous car yet without running into the human factor, not even pilot projects work out well. AI? Never. We're trolling it and having fun with it. It ain't gonna work.

Personally, I see this as AMD's Skylake. It's 'ground-up' (but, it's really not).
Let's just hope AMD doesn't get stuck on a single node for 4+ generations, too.

 

[Vayra86]

Personally, I see this as AMD's Skylake. It's 'ground-up' (but, it's really not).
Let's just hope AMD doesn't get stuck on a single node for 4+ generations, too.

Yeah, agreed

 

[atomsymbol]

Uh? I'm not complaining, just putting a slide's outings in perspective. Because many people read marketing and take it for granted, even the things often read as 'normal'. If you keep getting told something is truly revolutionary, it probably is, right? Meanwhile, after buying it you see minor improvements in performance and you might think 'hm... theory != reality'.

Well, but without knowledge of (and curiosity about) CPU architecture, any person is pretty much guaranteed to misinterpret any kind of marketing statement - even if the CPU marketing statement accurately reflects reality. I think, you should just concentrate on the architecture, on hard data, and ignore the rest.

 

[Vayra86]

Well, but without knowledge of (and curiosity about) CPU architecture, any person is pretty much guaranteed to misinterpret any kind of marketing statement - even if the CPU marketing statement accurately reflects reality. I think, you should just concentrate on the architecture, on hard data, and ignore the rest.

Hard data will say we'll see 10-20% perf improvements per tier, where 20% is near wishful thinking, so if that's the fruit of grounds-up, yeah, ok. We've put that in perspective nicely that way...

Meanwhile, GPUs do 'grounds-up' or just small refinements and push upwards of 30% per gen/tier. Because they can just expand a bit, doing parallel work, too. So you're right I guess, there's no value whatsoever in saying 'grounds-up'. It says nothing Wait... don't we actually agree then?

 

[atomsymbol]

Let's just hope AMD doesn't get stuck on a single node for 4+ generations, too.

That's not AMD's choice to make, because it has no fabs. That choice is being made by fabs, AMD follows fab's choice.

 

[maximumterror]

View attachment 349471

This leak here is much more interesting.
Lower TDP for ryzen 7 and slightly higher clocks.

uh baby! 9700X 65w!

 

[atomsymbol]

Hard data will say we'll see 10-20% perf improvements per tier, where 20% is near wishful thinking, so if that's the fruit of grounds-up, yeah, ok. We've put that in perspective nicely that way...

If you compare znver4 and znver5 in GCC compiler source code, then wishful thinking amounts exactly to 33%. Any smaller number than 33% is realistic, including 20%.

 

[Vayra86]

If you compare znver4 and znver5 in GCC compiler source code, then wishful thinking amounts exactly to 33%. Any smaller number than 33% is realistic, including 20%.

We'll see I hope so!

 

[Onasi]

If you compare znver4 and znver5 in GCC compiler source code, then wishful thinking amounts exactly to 33%. Any smaller number than 33% is realistic, including 20%.

True! But, I think, when people talk about percentile increases they, however subconsciously, mean in aggregate over a multitude of applications. Since we’re on TPU, let’s say in W1zz’s benchmark suite. I am sure that you can find instances where a new arch will be massively faster than a previous one (say, like supporting some new AVX extension in supported software) and ones where the difference is minimal. Overall, just like @Vayra86 said, gen to gen with architectural changes we see aggregate improvements in that 10-20% ballpark on average historically over the past decade and a half or so (let’s momentarily forget the Skylake regurgitation era) and there is good reasons to expect the same-ish results now.

 

[Vayra86]

True! But, I think, when people talk about percentile increases they, however subconsciously, mean in aggregate over a multitude of applications. Since we’re on TPU, let’s say in W1zz’s benchmark suite. I am sure that you can find instances where a new arch will be massively faster than a previous one (say, like supporting some new AVX extension in supported software) and ones where the difference is minimal. Overall, just like @Vayra86 said, gen to gen with architectural changes we see aggregate improvements in that 10-20% ballpark on average historically over the past decade and a half or so (let’s momentarily forget the Skylake regurgitation era) and there is good reasons to expect the same-ish results now.

It gets really funny if you're a gamer, too, our GPUs advance leaps and bounds faster than game CPU performance. The biggest uptick was a new API (DX12) The advances there come mostly from clockspeed, faster pipeline and software side improvements.

 

[Onasi]

It gets really funny if you're a gamer, too, our GPUs advance leaps and bounds faster than game CPU performance. The biggest uptick was a new API (DX12)

I stopped caring about CPU gaming performance a while ago, truth be told. Unless you are an e-sports fiend who desperately needs 600 frames to win a LAN CS tournament, for most of us who aren’t and are using reasonable hardware (so we aren’t talking 1500 bucks halo cards), any mid-range and up CPU from the past couple of generations is, essentially, good enough. In single player and non-competitive MP titles the benefits of going beyond 120 frames or so are hilariously small to the point of being nonexistent. As such, you are far more likely to be limited by your GPU in how much purrdy you can put on the screen rather than by your CPUs ability to keep up. And, unfortunately, it’s not like we see many games using the massive power of modern CPUs to do something really cool gameplay-wise. Last time that happened for me personally was the OG Supreme Commander… and that was a long time ago.
But I dunno, maybe someone out there still is mad that he can’t get beyond 1500 FPS in UT99, I’ve heard stranger.

 

[Denver]

If you had (which you don't) your own x86-64 CPU design, you made changes in multiple places in the core design, optimized the design, then "recompiled" the CPU design source code so that it is error free: wouldn't you yourself be claiming that it is a grounds-up redesign?

AMD has not invested billions in Zen, improving Branch-Predictor and the like to simply throw away. Zen5 will have major design changes compared to other generations, but the term GROUNDS-UP there is pure marketing...

 

[RandallFlagg]

Yeah about as fresh as Core by now, let's not fool each other here. Grounds-up, so they recompiled it. Great Its still a Zen CPU. Grounds-up means exactly nothing, or about as much as nanometer processes now.

Zen 1 was grounds-up. This is another Zen CPU

I agree with the sentiment, and from the standpoint of basic building blocks of a processor (not even a 'cpu') nothing has changed since the 1960s. Keller even referenced this not long ago, saying that the formulae for designing a processor is well known and nothing new has been added in 30 years. The biggest hurdle for them is defining what they want it to do, I think that's done at the microcode level, specific operations running faster, often based on testing mixes of different common applications and what they believe will be used in the future.

However, in my view real core architectural changes occur when you modify the width and/or depth of the pipeline, number and type of registers, add new microcode instructions. From that perspective, Zen 5 is the first really new core in the Zen lineup. Most of the changes since Zen 1 had to do with physical construction (CCDs), cache, and memory. The core functional design did not much change. Zen 5's core is different.

 

[MaMoo]

Boot time had nothing to do with the CPU, it was due to AM5 being a newer platform.

Mind you there's no need to "hope" for anything, that issue was fixed a long time ago.

I'm planning on building an AM5 + Zen 5 platform. I have no one around me who is using an AM5 computer. I have not had the opportunity to experience this issue before.

What's the current boot times for AM5? I'm genuinely curious if anyone is willing to share. FYI, I never timed it, but I guess I wait for about 10 to 15 seconds for a cold boot to get to the BIOS screen on my Intel computer with Alder Lake.

 

[Makaveli]

When will they learn to NOT do boring launches? No X3D chips?

This isn't any different from last gen. X3D cache is also going into server products which generate more money and are a higher priority. Would never see this launch at the same time consumer level is always lower priority.

 

[atomsymbol]

I agree with the sentiment, and from the standpoint of basic building blocks of a processor (not even a 'cpu') nothing has changed since the 1960s. Keller even referenced this not long ago, saying that the formulae for designing a processor is well known and nothing new has been added in 30 years. The biggest hurdle for them is defining what they want it to do, I think that's done at the microcode level, ...

It definitely isn't being "done at the microcode level". Maybe you meant a different term, not the term "microcode".

However, in my view real core architectural changes occur when you modify the width and/or depth of the pipeline, number and type of registers,

Zen5 (supposedly) increases "pipeline width" (that is actually: dispatch width) from 6 to 8.

add new microcode instructions.

That's definitely not the case.

From that perspective, Zen 5 is the first really new core in the Zen lineup. Most of the changes since Zen 1 had to do with physical construction (CCDs), cache, and memory. The core functional design did not much change. Zen 5's core is different.

The most significant advancement in CPU core architecture in recent years has been the ability to predict multiple branch instructions in a single clock cycle. Zen5 can be expected to be better than Zen4 in branch prediction, but the fact is that Zen4, as well as Intel CPUs, are already able to perform multiple branch predictions per cycle (not-taken branches). Intel Skymont CPU might (I am not saying that it will - it is still uncertain) be among the 1st CPUs to be able to predict 2 taken branches in a single clock cycle.

 

[RandallFlagg]

It definitely isn't being "done at the microcode level". Maybe you meant a different term, not the term "microcode".

Microcode is a layer below "Assembly". To perform a new microcode instruction, you have to change the circuitry. So no, I did not mean something different.

Zen5 (supposedly) increases "pipeline width" (that is actually: dispatch width) from 6 to 8.



That's definitely not the case.

Perhaps not for Zen 5.

The most significant advancement in CPU core architecture in recent years has been the ability to predict multiple branch instructions in a single clock cycle. Zen5 can be expected to be better than Zen4 in branch prediction, but the fact is that Zen4, as well as Intel CPUs, are already able to perform multiple branch predictions per cycle (not-taken branches). Intel Skymont CPU might (I am not saying that it will - it is still uncertain) be among the 1st CPUs to be able to predict 2 taken branches in a single clock cycle.

False. IBM had this ability in 1961, and several 'supercomputers' had it in the 70s. The DEC VAX had it in the late 80s. AFAIK, MIPS was the first to use it in smaller form factor servers/workstations.

It's gotten more sophisticated, but saying it didn't exist is about as uninformed as thinking that turbochargers didn't exist in cars until the last 15 years or so simply because most cars have them now.

There's nothing new about it.

 

[atomsymbol]

Microcode is a layer below "Assembly". To perform a new microcode instruction, you have to change the circuitry. So no, I did not mean something different.

You are misusing terminology.

False. IBM had this ability in 1961, and several 'supercomputers' had it in the 70s. The DEC VAX had it in the late 80s. AFAIK, MIPS was the first to use it in smaller form factor servers/workstations.

If the IBM CPU wasn't able to execute the equivalent of at least 5 x86 instructions per clock (because the length of a basic block is about 5 [x86] instructions), then it wasn't actually predicting multiple branches per cycle. What was the average IPC of the IBM CPU in 1961?

It's gotten more sophisticated, but saying it didn't exist is about as uninformed as thinking that turbochargers didn't exist in cars until the last 15 years or so simply because most cars have them now.

Please stop posting ridiculous analogies and start posting facts. What was the IPC of the IBM 1961 CPU? Which IBM CPU was it?

Microcode is a layer below "Assembly". To perform a new microcode instruction, you have to change the circuitry. So no, I did not mean something different.

Just because Grace Hopper used the "compiler" 50 years into the past doesn't mean that you can use the term today without adapting it - because the meaning of the term "compiler" is different today.

False. IBM had this ability in 1961, and several 'supercomputers' had it in the 70s. The DEC VAX had it in the late 80s. AFAIK, MIPS was the first to use it in smaller form factor servers/workstations.

If you mean IBM Stretch (7030 CPU): 1.2 MIPS, 2 MHz frequency, 9 programs (threads) in parallel => 1.2/2/9 = 0.06 instructions per clock (single-thread). No?

After taking a look in 7030 reference manual (http://www.bitsavers.org/pdf/ibm/7030/22-6530-2_7030RefMan.pdf): the year-1960 term "look-ahead" means "L1I and L1D cache" in today's terminology.

 

[Psychoholic]

Need some 12 or 16 core CCDs.. i know, that's a pipe dream.

 

[RandallFlagg]

<snip>



If you mean IBM Stretch (7030 CPU): 1.2 MIPS, 2 MHz frequency, 9 programs (threads) in parallel => 1.2/2/9 = 0.06 instructions per clock (single-thread). No?

Your extreme level of ignorance is on full display there sparky. Speed / performance is relative to many unrelated factors (materials tech, lithography), and has nothing to do with the use of "branch prediction". "IPC" is not and never has been related to "branch prediction". And to be clear, the 7030 was a "supercomputer" in 1961.

You're welcome for the education, welcome to my short but distinguished ignore list.

 

[atomsymbol]

Your extreme level of ignorance is on full display there sparky. Speed / performance is relative to many unrelated factors (materials tech, lithography), and has nothing to do with the use of "branch prediction". "IPC" is not and never has been related to "branch prediction". And to be clear, the 7030 was a "supercomputer" in 1961.

You're welcome for the education, welcome to my short but distinguished ignore list.

You are an old girl/guy who is incapable of learning today's terminology. I am sorry, I cannot help you.

"IPC" is not and never has been related to "branch prediction".

I think this is the most idiotic statement I have seen in many years.