Intel Intros 14th Gen Core "E" Embedded Processors with E-cores Disabled

[btarunr]

Intel introduced a line of 14th Gen Core "Raptor Lake Refresh" Socket LGA1700 processors for the embedded systems market. A highlight of these chips is that they come with their "Gracemont" E-core clusters disabled, and are pure P-core chips. It's interesting that Intel targets these chips for the embedded systems segment, but isn't building these in the non-socketed BGA packages carried over from its mobile platforms. Intel is addressing nearly all performance market-segments with these chips, including the very top. The Core i9-14901KE processor leading the pack is an 8-core/16-thread chip with eight "Raptor Cove" cores sharing the full 36 MB L3 cache available on the "Raptor Lake-S" die, a maximum boost frequency of 5.80 GHz, base frequency of 3.80 GHz, and processor base power of 125 W. The chip features an iGPU. The "K" in KE denotes that the chip supports overclocking.

Next up, is the Core i9-14901E, the 65 W sibling of this chip, which lacks an unlocked multiplier, and boosts up to 5.60 GHz, with a 2.80 GHz base frequency. Things get interesting with the Core i7-14701E, because the differentiator between the Core i9 and Core i7 SKUs is E-core count, and here we see the i7-14701 retaining the same 8-core/16-thread pure P-core configuration as the Core i9 chips, but with a touch lower frequencies of 5.40 GHz maximum boost, and 2.60 GHz base.



The Core i5-14501E is a 6-core/12-thread processor based on the larger "Raptor Lake-S" die, unlike the regular Core i5-14500 that uses the "Alder Lake-S" die. The 6 P-cores share 24 MB of L3 cache, and each feature 2 MB of dedicated L2 cache, unlike the i5-14500, which sees 1.25 MB of L2 cache per P-core, besides the 8 E-cores. This chip boosts up to 5.20 GHz, and has a base frequency of 3.30 GHz. The i5-14501TE is a variant of this chip with 45 W processor base power, 5.10 GHz maximum boost frequency, and 2.20 GHz base frequency.

Lastly, there are the Core i5-14401E, i5-14401EF, and the i5-14401TE. The first two are differentiated with the i5-14401EF lacking integrated graphics, the first two are 65 W chips, while the i5-14401TE is 45 W. The i5-14401E/EF boost up to 4.70 GHz, with a 2.50 GHz base frequency, while the i5-14401TE boosts up to 4.50 GHz, with a 2.00 GHz base frequency.

All chips in the 14th Gen Core E-series feature the same I/O as the regular 14th Gen Core desktop processors, with a PCI-Express 5.0 x16 PEG interface, a CPU-attached Gen 4 x4 NVMe interface, and a DMI 4.0 x8 chipset bus. The memory interface supports dual-channel DDR4 and DDR5 memory types.

View at TechPowerUp Main Site | Source

 

[usiname]

2 Years later and 2-4 P cores less than what it ahould have been

 

[Chaitanya]

Intel needs to perform durability testing of these i7 and i9 chips as well before milking more money out of customers.

 

[phanbuey]

yeah any new product introduction is useless without a guarantee that the issue is resolved.

 

[phints]

E-cores, more time wasted with cores that should be called PW-cores "Power Wasting" cores just like Intels trash hyperthreading.

 

[kondamin]

Would be nice if they replaced the gated Off parts with something that could serve as a heat sink

 

[Dr. Dro]

Intel needs to perform durability testing of these i7 and i9 chips as well before milking more money out of customers.

I agree, it's a rather bold move to release embedded segment products while facing stability problems. AMD didn't launch the Ryzen Embedded chips until late in socket AM4's life by the time most issues were resolved

Would be nice if they replaced the gated Off parts with something that could serve as a heat sink

Disabled/fused off parts generally act as dark silicon. It's why the -KF CPUs tend to be *slightly* better sometimes.

E-cores, more time wasted with cores that should be called PW-cores "Power Wasting" cores just like Intels trash hyperthreading.

What nonsense. SMT is trash as a whole, it's a technology which E-cores were designed to eclipse after all. Mind you, the higher the SMT yield means that your core gets stalled for longer, and thus is a less efficient design. Just keep that in mind before you gloat.

 

[Ruru]

What nonsense. SMT is trash as a whole, it's a technology which E-cores were designed to eclipse after all. Mind you, the higher the SMT yield means that your core gets stalled for longer, and thus is a less efficient design. Just keep that in mind before you gloat.

Wait, what? HT is what makes those old quad Intels still usable where the i5s start to became crap in anything than basic usage.

 

[Dr. Dro]

Wait, what? HT is what makes those old quad Intels still usable where the i5s start to became crap in anything than basic usage.

That's because they are old quad cores. The new Lion Cove P-core design removes hyper-threading support. It's no longer needed, CPUs have 24 cores now. Skymont has incredible IPC, almost as fast as Raptor Cove. Gracemont itself is not incompetent as some resentful people make it sound, each of these e-core clusters performs pretty much like a i7-6700K on their own. There's very little to gain in the way of processing speed for a big tradeoff in power efficiency and leaving a side-channel open for vulnerabilities. I expect AMD will do away with SMT on their processors eventually as well, once they have more than 8 cores per CCD.

 

[Ruru]

That's because they are old quad cores. The new Lion Cove P-core design removes hyper-threading support. It's no longer needed, CPUs have 24 cores now. There's very little to gain in the way of processing speed for a big tradeoff in power efficiency and leaving a side-channel open for vulnerabilities. I expect AMD will do away with SMT on their processors eventually as well, once they have more than 8 cores per CCD.

I still don't get that how SMT is a security threat

 

[Wirko]

What nonsense. SMT is trash as a whole, it's a technology which E-cores were designed to eclipse after all. Mind you, the higher the SMT yield means that your core gets stalled for longer, and thus is a less efficient design. Just keep that in mind before you gloat.

SMT is very unpredictable. You can find extreme cases where the gain is 100% (7-zip?) but sometimes it's around zero, a few % above or below. The scheduler can't analyse the code in depth so it could distribute the threads optimally.

 

[Sunny and 75]

the embedded systems market.

That's a bummer.

pure P-core chips.

Better late than never.

 

[Dr. Dro]

I still don't get that how SMT is a security threat

SMT works by redirecting instructions to an alternate "pipe" while a core is stalled waiting for either the next command or a response from system memory. It's a prime target for speculative execution and side channel exploits. The more time a core spends stalled (either due to exceptionally long pipeline stage, branch misprediction rate or slow memory, the higher will the SMT ratio be. Good read, even though it's a bit out of date by now:

Is Hyper-Threading a Fundamental Security Risk?

Has Intel's Hyper-Threading support become a fundamental security problem? Theo de Raadt, founder of OpenBSD, argues that it has.

www.extremetech.com

SMT is very unpredictable. You can find extreme cases where the gain is 100% (7-zip?) but sometimes it's around zero, a few % above or below. The scheduler can't analyse the code in depth so it could distribute the threads optimally.

That's because different types of workloads are processed in different ways by the processor. Some are extremely easy (basic math and word processing), others not so much.

 

[Evrsr]

I still don't get that how SMT is a security threat

Because it is fundamentally broken. If you don't understand side-channels, it is hard to grasp.

HT is always a permanent access to a side-channel on privileged processes, unless HT is disabled through instructions. You mostly can only use HT on the same process, which limits it's usefulness.

Before people freak out thinking that E-cores are broken, this is probably because some embedded systems are real-time and can't have Thread Director running around. At least not while it is in it's infancy.

Having a real-time scheduler is problematic enough as it is.

 

[AusWolf]

I agree, it's a rather bold move to release embedded segment products while facing stability problems. AMD didn't launch the Ryzen Embedded chips until late in socket AM4's life by the time most issues were resolved

Maybe Intel knows that it's the e-cores facing the stability problems, hence this "upgraded" half generation? (speculation)

 

[Sunny and 75]

e-cores facing the stability problems

Further investigation is required.

 

[Wirko]

Before people freak out thinking that E-cores are broken

Without implying E-cores are broken - they aren't broken - I can imagine someone could think up a side-channel attack on them. As long as they have shared resources (L2 and bus access), it's possible, although harder than on HT threads. And they have out-of-order execution too, which might be helpful to an attacker.

By the way, Skymont E-cores have a reorder buffer size of 416. Does this actually mean that an instruction (or a micro-op) can keep waiting while 415 other instructions are executed? That sounds quite incredible to me, reorder buffers and associated logic can't scale linearly with the buffer size, it's a n^2 relationship probably, or not?

 

[Sunny and 75]

each feature 2 MB of dedicated L2 cache

Finally!

 

[AnarchoPrimitiv]

"PEG interface"

Is that an Intel term? I get what they're referring to, but I've never seen it used anywhere else and a quick Google search really only returns one site thwt acknowledges its existence....an Intel site.

 

[Wirko]

yeah any new product introduction is useless without a guarantee that the issue is resolved.

The removal of the "K" alone solves the issue. Even in servers with W680 motherboards it's only K chips that are crashing.

Who the "overclockable embedded" chip is aimed at ... I have no idea.

 

[AnarchoPrimitiv]

I expect AMD will do away with SMT on their processors eventually as well, once they have more than 8 cores per CCD.

16 cores perchiplet? It's called Zen4c and Zen5c...AMD could have had one Zen4 chiplet and one Zen4c chiplet for a total of 24 cores...so why didn't AMD do that if you believe that path to be so "self-evident"? Why don't we have a R9 9975X with 8 Zen5 cores and 16 Zen5c cores for a total of 24 cores if that is the most logical path?

 

[Wirko]

"PEG interface"

Is that an Intel term? I get what they're referring to, but I've never seen it used anywhere else and a quick Google search really only returns one site thwt acknowledges its existence....an Intel site.

The term is very old but indeed always in relation to Intel hardware. But here is a mention from an AMD support person on an AMD forum mentioning PEG in BIOS settings.

 

[MaMoo]

16 cores perchiplet? It's called Zen4c and Zen5c...AMD could have had one Zen4 chiplet and one Zen4c chiplet for a total of 24 cores...so why didn't AMD do that if you believe that path to be so "self-evident"? Why don't we have a R9 9975X with 8 Zen5 cores and 16 Zen5c cores for a total of 24 cores if that is the most logical path?

Does it have something to do with Zen's much wider design? It seems to me that more parallelism can be extracted on Zens than with Intel's port-heavy design? So multithreading is more probabilistically symmetric in AMD's case?

 

[Sunny and 75]

Who the "overclockable embedded" chip is aimed at ... I have no idea.

That's the top SKU in the lineup for the top SKU buyers.

 

[JustBenching]

for a total of 24 cores if that is the most logical path?

$$

Why sell bigger dies for the same amount that you can sell smaller dies?

You need to realize, desktop chips are an afterthought for both amd and intel, we aren't really getting the best product possible, we are only getting whatever is leftover from servers and laptops. Especially on the AMD side with their ccd approach.