Intel Intros 14th Gen Core "E" Embedded Processors with E-cores Disabled

[AusWolf]

I feel Intel is very insensitive to the issue surrounding their Raptor Lake CPUs now by introducing new SKUs. The CPUs are unstable, which means it is not functioning properly, which may potentially impact these new SKUs. Without addressing and resolving the existing issue, are they expecting people to buy these?

Unless it's a silent admission that the problem is with the e-cores, and they just want to keep selling something instead of doing a recall. (speculation)

 

[ratirt]

Can you guys say with 100% certainty, that the ecore are broken or malfunctioning thus being cut out or Intel's decision was not to use them even though they are OK?
I did not see the article say these are broken or defective. Maybe, these are not defective and the reason Intel disables the cluster is different than the obvious one 'defective cores'.

 

[AusWolf]

Can you guys say with 100% certainty, that the ecore are broken or malfunctioning thus being cut out or Intel's decision was not to use them even though they are OK?
I did not see the article say these are broken or defective. Maybe, these are not defective and the reason Intel disables the cluster is different than the obvious one 'defective cores'.

That's equally possible. That's why I wrote "speculation" in brackets. Until Intel does an official announcement, or someone does a thorough investigation, we won't know for sure.

 

[joemama]

Why would Intel intentionally turn off some cores to sell their product with a lower price? Only reviving defective chips would make sense

 

[watzupken]

Unless it's a silent admission that the problem is with the e-cores, and they just want to keep selling something instead of doing a recall. (speculation)

I am not too sure about it. The ability to disable E-cores is already available. So it is not difficult for reviewers or investigators to find out the issue. Regardless, if Intel is not confirming the issue, all the more people should avoid anything to do with Raptor Lake.

 

[Dr. Dro]

Are these fused off silicon ? or the E-core spaces just empty ?

Fused off.

Silicon that is disabled, but is nevertheless present on the chip and is otherwise fully functional, is a waste of natural resources and a waste of chip manufacturing capacity.

Quite contrary. Chip harvesting allows imperfect processor dies to be sold as otherwise fully functioning processors. If you own a Core i7 or i5, or a Ryzen 5/Ryzen 9 x900 series, you have a harvest in your hands.

I am not too sure about it. The ability to disable E-cores is already available. So it is not difficult for reviewers or investigators to find out the issue.

CPU manufacturing is a very complicated process, and imperfections can be present in any area of the processor. This one has the four e-core clusters and associated L2 cache disabled. What's interesting is that the full L3 slice is enabled on the 14901KE, which may mean that the L3 cache that is normally attribute to an e-core cluster is not necessarily an inherent part of it and can be accessed by the P-cores normally.

 

[InVasMani]

Fused off.



Quite contrary. Chip harvesting allows imperfect processor dies to be sold as otherwise fully functioning processors. If you own a Core i7 or i5, or a Ryzen 5/Ryzen 9 x900 series, you have a harvest in your hands.



CPU manufacturing is a very complicated process, and imperfections can be present in any area of the processor. This one has the four e-core clusters and associated L2 cache disabled. What's interesting is that the full L3 slice is enabled on the 14901KE, which may mean that the L3 cache that is normally attribute to an e-core cluster is not necessarily an inherent part of it and can be accessed by the P-cores normally.

If you disable E-cores it negates a bunch of added strain off the Ring by extension because L3 cache is connected with Ring and accessible by the E-cores. I don't believe there is a bios to enable L3 cache access only to P cores or not that I know of on my Asus board at least. I wonder if they could even implement a bios option to limit a ratio of how much access to L3 E-cores can receive if it's creating problems in heavy MT scenario's. The only conclusions I have is these chips are really sensitive in terms of stability given how far they've been pushed and with how many cores they include. Plus there are other outside conditions complicating matters like MB makers defaults adding fuel to the fire.

I tried to dig for a few voltage spec settings in Intel's PDF of 13th/14th gen, but they didn't seem to provided it for L2 cache voltage and cache voltage. It would be nice to know what's minimum, typical, max on those yet I couldn't find those details and I tried.

 

[kondamin]

Can you guys say with 100% certainty, that the ecore are broken or malfunctioning thus being cut out or Intel's decision was not to use them even though they are OK?
I did not see the article say these are broken or defective. Maybe, these are not defective and the reason Intel disables the cluster is different than the obvious one 'defective cores'.

From all that I have been reading is that intel has pushed intel 7 to hard which is making the k parts rip them selves apart.

wouldnt surprise me one bit that if the p cores were disabled the chips that are crashing now would stop crashing as the e cores aren’t clocked to stupid speeds.

 

[iameatingjam]

From all that I have been reading is that intel has pushed intel 7 to hard which is making the k parts rip them selves apart.

wouldnt surprise me one bit that if the p cores were disabled the chips that are crashing now would stop crashing as the e cores aren’t clocked to stupid speeds.

ironically, it was the exact opposite for me, the only way I could make my 14700k boot was to disable at least 8 ecores. But thats one anecdotal case and we're hearing so much stuff right now its hard to know what is what.... the failures don't exactly follow a neat pattern. Which is why is we need some communication from intel. All we seem to know for sure is that higher clocks and higher voltages make it worse/speed it up, whatever the root problem is, maybe there's more than one root problem.

 

[AusWolf]

wouldnt surprise me one bit that if the p cores were disabled the chips that are crashing now would stop crashing as the e cores aren’t clocked to stupid speeds.

But they're a lot smaller (and maybe denser?) as well, so what doesn't seem like a stupidly high clock speed for p-cores could very well be one for e-cores.

 

[Wirko]

Quite contrary. Chip harvesting allows imperfect processor dies to be sold as otherwise fully functioning processors. If you own a Core i7 or i5, or a Ryzen 5/Ryzen 9 x900 series, you have a harvest in your hands.

Sure, but as the process matures, yields improve all the time. No one is willing to disclose any specific data, just some relative info like in this example graph (let's assume it's zero-based):



And then there are estimates by analysts such as TrendForce:

At present, the production yield rate of Sapphire Rapids is estimated at only 50~60%, which affects mainstream Sapphire Rapids MCC products. [November 2022]

which doesn't tell us the most basic thing - are the bad chips totally unusable, or do they just have a small number of bad cores out of 34?

2.5 years into Intel 7 manufacturing, I'd say it would be very bad for Intel if less than 50% of the CPUs on a Raptor Lake wafer were operative - I mean fully operative, with zero defects. They can't sell that many i9-13900/14900 chips (despite countless suffixes) because those all cost 440€ and up. So they still have to disable some good parts.

CPU manufacturing is a very complicated process, and imperfections can be present in any area of the processor. This one has the four e-core clusters and associated L2 cache disabled. What's interesting is that the full L3 slice is enabled on the 14901KE, which may mean that the L3 cache that is normally attribute to an e-core cluster is not necessarily an inherent part of it and can be accessed by the P-cores normally.

The same is true of the other chips in this new series, see my post #42. Interestingly, the two disabled P cores in the 14501E also have their L3 slices inoperative.

the failures don't exactly follow a neat pattern. Which is why is we need some communication from intel. All we seem to know for sure is that higher clocks and higher voltages make it worse/speed it up, whatever the root problem is, maybe there's more than one root problem.

Exactly. I'd even suspect the power delivery system on the chip (and substrate too) first, which would mean that you can't pin the flaw to any of the cores.

 

[atomsymbol]

Quite contrary. Chip harvesting allows imperfect processor dies to be sold as otherwise fully functioning processors. If you own a Core i7 or i5, or a Ryzen 5/Ryzen 9 x900 series, you have a harvest in your hands.

It is extremely unlikely for chip manufacturing defects governed by laws of physics and chemistry to perfectly match (1) AMD/Intel's market segmentation, (2) market demand or (3) distribution of wealth in a society. ---- I mean it in the following sense: If AMD/Intel were serious about conserving Earth's resources and were selling what was manufactured, then for example Intel would be selling a CPU configuration like 5*Pcore + 1*Ecore and AMD would be selling 7*Zen4 CPUs.

 

[Dr. Dro]

It is extremely unlikely for chip manufacturing defects governed by laws of physics and chemistry to perfectly match (1) AMD/Intel's market segmentation, (2) market demand or (3) distribution of wealth in a society. ---- I mean it in the following sense: If AMD/Intel were serious about conserving Earth's resources and were selling what was manufactured, then for example Intel would be selling a CPU configuration like 5*Pcore + 1*Ecore and AMD would be selling 7*Zen4 CPUs.

I agree but once you account for the sheer volume and intended market channels, it lines up. If demand exceeds supply by a significant margin then they will intentionally cap better CPUs to meet spec.

 

[atomsymbol]

If demand exceeds supply by a significant margin then they will intentionally cap better CPUs to meet spec.

It is a valid approach. However, there exist alternative approaches.

It is fairly simple in a market economy to correct a demand-exceeds-supply disequilibrium: gradually increase prices in order for demand to match manufacturing capacity.

The other way around: When supply-exceeds-demand, gradually lower prices in order for demand to match manufacturing capacity.

If prices aren't increased/decreased gradually (that is: are increased/decreased sharply) it creates a very high risk of unhealthy oscillations in the economy. For example, search for "prey predator model dampening" in Google Images.

 

[Evrsr]

No what you're talking about is OoO not just SMT ~ to disable all possible side channel attacks you'd have to go back to the stone ages!

No OoO exec you can manage, as it is easier to stop speculation for which there is no privilege to access the data. This has already been implemented and the other situations where you don't want speculation for secure processes (memory re-ordering), this can be disabled for those.

With SMT, you can't really run secure processes on shared core and it costs die space and increases complexity. The OS has to make sure to not schedule two processes on the same core, so it quickly looses usefulness. Stuff servers want to run become severely limited, like virtual machines, web servers, encryption, etc.

OoO is also subject to this to some extent but the performance is worth the trouble, as it increases 3, 4 or 5x. I will say the future is looking like multithreading be powered by secure and isolated efficient cores. This is already mostly the case for Intel and ARM.