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A CPU-Z screenshot of an alleged Intel Core Ultra 9 285K "Arrow Lake-S" desktop processor engineering sample is doing rounds on social media, thanks to wxnod. CPU-Z identifies the chip with an Intel Core Ultra case badge with the deep shade of blue associated with the Core Ultra 9 brand extension, which hints at this being the top Core Ultra 9 285K processor model, we know it's the "K" or "KF" SKU looking at its processor base power reading of 125 W. The chip is built in the upcoming Intel Socket LGA1851. CPU-Z displays the process node as 7 nm, which corresponds with the Intel 4 foundry node.
Intel is using the same Intel 4 foundry node for "Arrow Lake-S" as the compute tile of its "Meteor Lake" processor. Intel 4 offers power efficiency and performance comparable to 4 nm nodes from TSMC, although it is physically a 7 nm node. Likewise, the Intel 3 node is physically 5 nm. If you recall, the main logic tile of "Lunar Lake" is being built on the TSMC N3P (3 nm) node. This means that Intel is really gunning for performance/Watt with "Lunar Lake," to get as close to the Apple M3 Pro as possible.
"Arrow Lake" features the same "Lion Cove" P-cores and "Skymont" E-cores as "Lunar Lake," but connected differently. In "Lunar Lake," the P-core complex sits on its own tiny ringbus with an exclusive L3 cache; with the E-core clusters being separated into low-power islands. The two core types talk to each other over the chip's high bandwidth fabric. In "Arrow Lake," however, the "Lion Cove" P-cores and "Skymont" E-core clusters share a ringbus and L3 cache, like the two core types do on current "Raptor Lake" chips. Intel will innovate with the way the P-cores and E-core clusters are physically arranged along the ringbus, and you can read all about it in our older article.
Back to the CPU-Z screenshot, and we're shown a clock speed of 5.00 GHz. This is likely being read off the first "Lion Cove" P-core. The P-cores have 48 KB of L1 Data (L1D) and 64 KB of L1 Instructions (L1I) caches; while the E-cores have 32 KB of L1D and 64 KB of L1I caches. We've known since the "Lunar Lake" technical deep-dive from Intel's comments, that the "Lion Cove" P-cores on "Arrow Lake" will get 3 MB of dedicated L2 caches, compared to 2.5 MB per core on "Lunar Lake." Each of the four "Skymont" E-core clusters of "Arrow Lake" shares 4 MB of L2 cache among the four cores in the cluster.
The total L2 cache on "Arrow Lake-S" is 40 MB. This is from eight 3 MB caches from the P-cores, and four 4 MB caches from the E-core clusters (24 MB + 16 MB). We are now learning that the shared L3 cache size remains 36 MB on "Arrow Lake."
Since the "Lion Cove" P-cores lack HyperThreading, "Arrow Lake-S" is a 24-core/24-thread processor. The generational performance gain over the current Core i9-14900K will boil down to the ~14% IPC gain of "Lion Cove" over "Redwood Cove" (which in-turn was within 2% of "Raptor Cove"); and the massive 38-68% IPC improvement of the "Skymont" E-core over the "Crestmont" E-core (which in turn was +8% over "Gracemont.").
Intel is expected to debut the Core Ultra 200 series "Arrow Lake-S" desktop processors, and the LGA1851 platform led by the Intel Z890 chipset, around late-September or early-October, 2024.
View at TechPowerUp Main Site | Source
Intel is using the same Intel 4 foundry node for "Arrow Lake-S" as the compute tile of its "Meteor Lake" processor. Intel 4 offers power efficiency and performance comparable to 4 nm nodes from TSMC, although it is physically a 7 nm node. Likewise, the Intel 3 node is physically 5 nm. If you recall, the main logic tile of "Lunar Lake" is being built on the TSMC N3P (3 nm) node. This means that Intel is really gunning for performance/Watt with "Lunar Lake," to get as close to the Apple M3 Pro as possible.
"Arrow Lake" features the same "Lion Cove" P-cores and "Skymont" E-cores as "Lunar Lake," but connected differently. In "Lunar Lake," the P-core complex sits on its own tiny ringbus with an exclusive L3 cache; with the E-core clusters being separated into low-power islands. The two core types talk to each other over the chip's high bandwidth fabric. In "Arrow Lake," however, the "Lion Cove" P-cores and "Skymont" E-core clusters share a ringbus and L3 cache, like the two core types do on current "Raptor Lake" chips. Intel will innovate with the way the P-cores and E-core clusters are physically arranged along the ringbus, and you can read all about it in our older article.
Back to the CPU-Z screenshot, and we're shown a clock speed of 5.00 GHz. This is likely being read off the first "Lion Cove" P-core. The P-cores have 48 KB of L1 Data (L1D) and 64 KB of L1 Instructions (L1I) caches; while the E-cores have 32 KB of L1D and 64 KB of L1I caches. We've known since the "Lunar Lake" technical deep-dive from Intel's comments, that the "Lion Cove" P-cores on "Arrow Lake" will get 3 MB of dedicated L2 caches, compared to 2.5 MB per core on "Lunar Lake." Each of the four "Skymont" E-core clusters of "Arrow Lake" shares 4 MB of L2 cache among the four cores in the cluster.
The total L2 cache on "Arrow Lake-S" is 40 MB. This is from eight 3 MB caches from the P-cores, and four 4 MB caches from the E-core clusters (24 MB + 16 MB). We are now learning that the shared L3 cache size remains 36 MB on "Arrow Lake."
Since the "Lion Cove" P-cores lack HyperThreading, "Arrow Lake-S" is a 24-core/24-thread processor. The generational performance gain over the current Core i9-14900K will boil down to the ~14% IPC gain of "Lion Cove" over "Redwood Cove" (which in-turn was within 2% of "Raptor Cove"); and the massive 38-68% IPC improvement of the "Skymont" E-core over the "Crestmont" E-core (which in turn was +8% over "Gracemont.").
Intel is expected to debut the Core Ultra 200 series "Arrow Lake-S" desktop processors, and the LGA1851 platform led by the Intel Z890 chipset, around late-September or early-October, 2024.
View at TechPowerUp Main Site | Source
