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Software | Windows 11 Pro |
AMD's next generation RDNA 4 graphics architecture will see the company focus on the performance segment of the market. The company is rumored to not be making a successor to the enthusiast-segment "Navi 21" and "Navi 31" chips based on RDNA 4, and will instead focus on improving performance and efficiency in the most high-volume segments, just like the original RDNA-powered generation, the Radeon RX 5000 series. There are two chips in the new RDNA 4 generation that have hit the rumor mill, the "Navi 48" and the "Navi 44." The "Navi 48" is the faster of the two, powering the top SKUs in this generation, while the "Navi 44" is expected to be the mid-tier chip.
According to Kepler_L2, a reliable source with GPU leaks, and VideoCardz, which connected the tweet to the RDNA 4 generation, the top "Navi 48" silicon is expected to feature a 256-bit wide GDDR6 memory interface—so there's no upgrade to GDDR7. The top SKU based on this chip, the "Navi 48 XTX," will feature a memory speed of 20 Gbps, for 640 GB/s of memory bandwidth. The next-best SKU, codenamed "Navi 48 XT," will feature a slightly lower 18 Gbps memory speed at the same bus-width, for 576 GB/s of memory bandwidth. The "Navi 44" chip has a respectable 192-bit wide memory bus, and its top SKU will feature a 19 Gbps speed, for 456 GB/s of bandwidth on tap.
Another set of rumors from the same sources also point to the Infinity Cache sizes of these chips. "Navi 48" comes with 64 MB of it, which will be available on both the "Navi 48 XTX" and "Navi 48 XT," while the "Navi 44" silicon comes with 48 MB of it. We are hearing from multiple sources that the "Navi 4x" GPU family will stick to traditional monolithic silicon designs, and not venture out into chiplet disaggregation like the company did with the "Navi 31" and the "Navi 32."
Yet another set of rumors, these from Moore's Law is Dead, talk about how AMD's design focus with RDNA 4 will be to ace performance, performance-per-Watt, and performance cost of ray tracing, in the segments of the market that NVIDIA makes the most volumes in, if not the most margins in. MLID points to the likelihood of the ray tracing performance improvements riding on there being not one, but two ray accelerators per compute unit, with a greater degree of fixed-function acceleration for the ray tracing workflow (i.e. less of it will be delegated to the programmable shaders).
View at TechPowerUp Main Site | Source
According to Kepler_L2, a reliable source with GPU leaks, and VideoCardz, which connected the tweet to the RDNA 4 generation, the top "Navi 48" silicon is expected to feature a 256-bit wide GDDR6 memory interface—so there's no upgrade to GDDR7. The top SKU based on this chip, the "Navi 48 XTX," will feature a memory speed of 20 Gbps, for 640 GB/s of memory bandwidth. The next-best SKU, codenamed "Navi 48 XT," will feature a slightly lower 18 Gbps memory speed at the same bus-width, for 576 GB/s of memory bandwidth. The "Navi 44" chip has a respectable 192-bit wide memory bus, and its top SKU will feature a 19 Gbps speed, for 456 GB/s of bandwidth on tap.
Another set of rumors from the same sources also point to the Infinity Cache sizes of these chips. "Navi 48" comes with 64 MB of it, which will be available on both the "Navi 48 XTX" and "Navi 48 XT," while the "Navi 44" silicon comes with 48 MB of it. We are hearing from multiple sources that the "Navi 4x" GPU family will stick to traditional monolithic silicon designs, and not venture out into chiplet disaggregation like the company did with the "Navi 31" and the "Navi 32."
Yet another set of rumors, these from Moore's Law is Dead, talk about how AMD's design focus with RDNA 4 will be to ace performance, performance-per-Watt, and performance cost of ray tracing, in the segments of the market that NVIDIA makes the most volumes in, if not the most margins in. MLID points to the likelihood of the ray tracing performance improvements riding on there being not one, but two ray accelerators per compute unit, with a greater degree of fixed-function acceleration for the ray tracing workflow (i.e. less of it will be delegated to the programmable shaders).
View at TechPowerUp Main Site | Source