SK Hynix Develops Industry's First 1c (10nm-class) DDR5 Memory

[btarunr]

SK hynix announced today that it has developed the industry's first 16 Gb DDR5 built using its 1c node, the sixth generation of the 10 nm process. The success marks the beginning of the extreme scaling to the level closer to 10 nm in the memory process technology. The degree of difficulty to advance the shrinking process of the 10 nm-range DRAM technology has grown over generations, but SK hynix has become the first in the industry to overcome the technological limitations by raising the level of completion in design, thanks to its industry-leading technology of the 1b, the fifth generation of the 10 nm process.

SK hynix said it will be ready for mass production of the 1c DDR5 within the year to start volume shipment next year. In order to reduce potential errors stemming from the procedure of advancing the process and transfer the advantage of the 1b, which is widely applauded for its best performing DRAM, in the most efficient way, the company extended the platform of the 1b DRAM for development of 1c. The new product comes with an improvement in cost competitiveness, compared with the previous generation, by adopting a new material in certain process of the extreme ultraviolet, or EUV, while optimizing the EUV application process of total. SK hynix also enhanced productivity by more than 30% through technological innovation in design.



The operating speed of the 1c DDR5, expected to be adopted for high-performance data centers, is improved by 11% from the previous generation, to 8 Gbps. With power efficiency also improved by more than 9%, SK hynix expects adoption of 1c DRAM to help data centers reduce the electricity cost by as much as 30% at a time when advancement of AI era is leading to an increase in power consumption.

"We are committed to providing differentiated values to customers by applying the 1c technology equipped with the best performance and cost competitiveness to our major next-generation products including HBM, LPDDR6, and GDDR7," said Head of DRAM Development Kim Jonghwan. "We will continue to work towards maintaining the leadership in the DRAM space and position as the most-trusted AI memory solution provider."

View at TechPowerUp Main Site

 

[JWNoctis]

For some interesting reading, look up "DRAM cell aspect ratio."

It's one of the major reasons why DRAM does not scale well anymore.

 

[hsew]

For some interesting reading, look up "DRAM cell aspect ratio."

It's one of the major reasons why DRAM does not scale well anymore.

Basically, 3D DRAM can’t come quick enough.

 

[Wirko]

Basically, 3D DRAM can’t come quick enough.

You may know this article:

Will Monolithic 3D DRAM Happen?

New and faster memory designs are being developed, but their future is uncertain.

semiengineering.com

It's a nice but 3 year old overview of experimental technologies, and not much has come out since. (I follow SemiEngineering semi-regularly.) Yes, big playeres have announced 3D DRAM, without a timeline. They're somehow trying to adapt 3D NAND manufacturing process for DRAM.

A normal DRAM cell with a capacitor is actually very large, not by surface area but by volume, because it's deep. In 3D you can somehow turn the capacitors on the side but then you get very low density per layer. But other ideas exist too, which get rid of capacitors.

And here's one thing I'm thinking about ... a 6-transistor static RAM cell is about 12x the size of a DRAM cell by area. But in a 3D layered design, a SRAM cell might actually be smaller by volume! Or at least have a size that can compete. One of the main problems of course is the fact that transistors built in layers have far worse performance than those built on substrate. Further, the interconnects can't be made in just any sort of complex pattern you may need.

This is interesting too ... it describes a DRAM cell that can store an analog value and do analog multiply-accumulate calculations.

Edit: And to make it clearer, the 3D DRAM mentioned here at Tom's for example, isn't really that. Although it's going to have 3D transistors (finfet or something similar), the memory cells will still be built in one layer on the wafer.