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Software | Windows 11 Pro |
AMD "Strix Halo" isn't just a mobile processor with an oversized iGPU meant to power "gaming ultraportables," it has other potential applications such as game consoles (both handheld and standalone). Not willing to cede this market to AMD, Intel is reportedly readying its own such chip, which is being reported as the "Arrow Lake Halo" for the lack of an official name. This chip will feature a large iGPU based on the Xe2 "Battlemage" graphics architecture, the variant of Xe2 Intel plans to use for its next-generation Arc discrete GPUs. The CPU compute complex will be carried over from the regular "Arrow Lake" chips, and feature a mix of "Lion Cove" P-cores, and "Skymont" E-core clusters.
To meet the higher memory bandwidth demand that arises from a high-performance iGPU and CPU, AMD designed the RDNA 3.5 graphics architecture to be more LPDDR5-aware, since at the physical layer, LPDDR operates differently from GDDR. Intel will probably do something similar, and deploy a 256-bit wide LPDDR5/x memory interface replacing the 128-bit wide interface the regular "Arrow Lake" mobile chips come with. Whether "Arrow Lake Halo" and "Strix Halo" remain competitive will depend a lot on which gaming experiences the two companies want to sell. The way the iGPU of "Strix Halo" is rumored to be specced suggests something that is 1440p-capable, or 4K-capable with FSR 3.
The oldest references to the "Arrow Lake Halo" date back to a purported Intel internal slide leaked to the web by Adored TV some time between 2021-2023, which used the "GT3" performance designator for the iGPU, and explicitly used the word "Halo" in its codename. The slide describes the chip as having 6 "Lion Cove" P-cores, and 8 "Skymont" E-cores, with a large iGPU. Such a product, however, may not end up competitive to what "Strix Halo" is shaping up to be—up to 16 full-sized "Zen 5" CPU cores, and an RDNA 3.5 iGPU with 40 compute units (2,560 stream processors). This to us suggests that the latest leak of "Arrow Lake Halo" is different from the one in the Adored TV leak, and may have more cores, and a larger iGPU.
This wouldn't be the first time Intel tried its hand at mobile processors with oversized iGPUs on the package, the "Kaby Lake-G" mobile processor featured a "Kaby Lake" CPU die and a Radeon Vega M GPU die sharing a package as an MCM, with the two dies having their own discrete memory interfaces.
Many Thanks to TumbleGeorge for the tip.
View at TechPowerUp Main Site | Source
To meet the higher memory bandwidth demand that arises from a high-performance iGPU and CPU, AMD designed the RDNA 3.5 graphics architecture to be more LPDDR5-aware, since at the physical layer, LPDDR operates differently from GDDR. Intel will probably do something similar, and deploy a 256-bit wide LPDDR5/x memory interface replacing the 128-bit wide interface the regular "Arrow Lake" mobile chips come with. Whether "Arrow Lake Halo" and "Strix Halo" remain competitive will depend a lot on which gaming experiences the two companies want to sell. The way the iGPU of "Strix Halo" is rumored to be specced suggests something that is 1440p-capable, or 4K-capable with FSR 3.
The oldest references to the "Arrow Lake Halo" date back to a purported Intel internal slide leaked to the web by Adored TV some time between 2021-2023, which used the "GT3" performance designator for the iGPU, and explicitly used the word "Halo" in its codename. The slide describes the chip as having 6 "Lion Cove" P-cores, and 8 "Skymont" E-cores, with a large iGPU. Such a product, however, may not end up competitive to what "Strix Halo" is shaping up to be—up to 16 full-sized "Zen 5" CPU cores, and an RDNA 3.5 iGPU with 40 compute units (2,560 stream processors). This to us suggests that the latest leak of "Arrow Lake Halo" is different from the one in the Adored TV leak, and may have more cores, and a larger iGPU.
This wouldn't be the first time Intel tried its hand at mobile processors with oversized iGPUs on the package, the "Kaby Lake-G" mobile processor featured a "Kaby Lake" CPU die and a Radeon Vega M GPU die sharing a package as an MCM, with the two dies having their own discrete memory interfaces.
Many Thanks to TumbleGeorge for the tip.
View at TechPowerUp Main Site | Source