Intel Clearwater Forest Pictured, First 18A Node High Volume Product

[AleksandarK]

Yesterday, Intel launched its Xeon 6 family of server processors based on P-cores manufactured on Intel 3 node. While the early reviews seem promising, Intel is preparing a more advanced generation of processors that will make or break its product and foundry leadership. Codenamed "Clearwater Forest," these CPUs are expected to be the first high-volume production chips based on the Intel 18A node. We have pictures of the five-tile Clearwater Forest processor thanks to Tom's Hardware. During the Enterprise Tech Tour event in Portland, Oregon, Tom's Hardware managed to take a picture of the complex Clearwater Forest design. With compute logic built on 18A, this CPU uses Intel's 3-T process technology, which serves as the foundation for the base die, marking its debut in this role. Compute dies are stacked on this base die, making the CPU building more complex but more flexible.

The Foveros Direct 3D and EMIB technologies enable large-scale integration on a package, achieving capabilities that previous monolithic single-chip designs could not deliver. Other technologies like RibbonFET and PowerVia will also be present for Clearwater Forest. If everything continues to advance according to plan, we expect to see this next-generation CPU sometime next year. However, it is crucial to note that if this CPU shows that the high-volume production of Intel 18A is viable, many Intel Foundry customers would be reassured that Intel can compete with TSMC and Samsung in producing high-performance silicon on advanced nodes at scale.



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[Vayra86]

That's effin huge

 

[londiste]

Wasn't Clearewater Forest envisioned to have 3x4 compute dies? On the picture the middle ones seem to be 3 long rectangular dies.

 

[SOAREVERSOR]

That's effin huge

What's old is new again! Back in ye olden days IBM POWER and some Sun SPARC CPUs were that big and had massive IHS at times with the liquid cooling connectors built in. IIRC IBM still cranks out some chips that size.

 

[docnorth]

...that will make or break its product and foundry leadership. The comment was really insightful, it's indeed a make or break situation for Intel (if not do or die).

 

[Philaphlous]

Yea that first pic of the person holding the CPU is definitely fake...not the person the chip. Just look how uneven the surface is, not even mirror finish. Second, look at how the lines aren't even straight on the die shot...definitely fake. Maybe its a prototype for cooler design without actual silicon....not sure but I wouldn't go near the thing if this is real....

 

[Wirko]

I remember a photo from some event where Lisa Su was proudly showing off a CPU with obvious remains of black sealant. Nice to see Intel copying that little detail.

 

[SOAREVERSOR]

I remember a photo from some event where Lisa Su was proudly showing off a CPU with obvious remains of black sealant. Nice to see Intel copying that little detail.

But does it have wood screws?

 

[ncrs]

Wasn't Clearewater Forest envisioned to have 3x4 compute dies? On the picture the middle ones seem to be 3 long rectangular dies.

That was an early 3D render if you're referencing this:

It might be internally split into sub-clusters as well since it's expected to have a lot of cores. There's also 3 big dies visible on the render. We'll have to wait for the official announcement.

Yea that first pic of the person holding the CPU is definitely fake...not the person the chip. Just look how uneven the surface is, not even mirror finish. Second, look at how the lines aren't even straight on the die shot...definitely fake. Maybe its a prototype for cooler design without actual silicon....not sure but I wouldn't go near the thing if this is real....

There's more photos of the entire family from ServeTheHome, and a better photo of Clearwater Forest too which doesn't have the artifacts you describe (which might simply be some phone camera AI processing). They are from a physical event by Intel, so I doubt they are fake

 

[tommo1982]

Which version of Foveros did Intel use?

 

[Minus Infinity]

Yea that first pic of the person holding the CPU is definitely fake...not the person the chip. Just look how uneven the surface is, not even mirror finish. Second, look at how the lines aren't even straight on the die shot...definitely fake. Maybe its a prototype for cooler design without actual silicon....not sure but I wouldn't go near the thing if this is real....

At worst, it is a mock-up of the actual SoC or a prototype.

 

[Scrizz]

Yea that first pic of the person holding the CPU is definitely fake...not the person the chip. Just look how uneven the surface is, not even mirror finish. Second, look at how the lines aren't even straight on the die shot...definitely fake. Maybe its a prototype for cooler design without actual silicon....not sure but I wouldn't go near the thing if this is real....

It's probably some sort of TIM. This is definitely some early test sample.

 

[Caring1]

Yea that first pic of the person holding the CPU is definitely fake...not the person the chip. Just look how uneven the surface is, not even mirror finish. Second, look at how the lines aren't even straight on the die shot...definitely fake. Maybe its a prototype for cooler design without actual silicon....not sure but I wouldn't go near the thing if this is real....

Lol no, if you look closely you can see the silicon used to hold the IHS to the chip.

 

[MiguelXTK]

Wasn't Clearewater Forest envisioned to have 3x4 compute dies? On the picture the middle ones seem to be 3 long rectangular dies.

Back Side Power Delivery Network AKA PowerVIA DIEs over 4cpu Chiplets (every chiplet 24 cores). Front Side is only 1 silicon. Back Side are 2 "glued", polish first for a perfect contact.

"Intel’s backside power solution is called PowerVia,.... Throw out pizza-making. For the first time, chipmaking is going two-sided.

Here’s how it works: Transistors are built first, as before, with the interconnect layers added next. Now the fun part: flip over the wafer and “polish everything off,”

Which version of Foveros did Intel use?

Foveros Direct 3D 9 microns bump pitch (vs 25 microns Foveros Omni) + EMIB = EMIB 3.5D

 

[tommo1982]

Foveros Direct 3D 9 microns bump pitch (vs 25 microns Foveros Omni) + EMIB = EMIB 3.5D

So they delivered on their promises from 2023. I'm curious what the performance will be when they launch, compared to Epyc.

 

[MiguelXTK]

So they delivered on their promises from 2023. I'm curious what the performance will be when they launch, compared to Epyc.

I want to see the performance with "main SRAM" (=Cache) on the Base DIE's (Intel 3-T= Intel 3 + Trough Silicon Vias AKA TSV + Foveros Direct 3D copper-to-copper 9 microns pitch) + Top DIE's Intel 18A with PowerVIA & RibbonFET.

Clearwater is= Intel 7 (IO Tiles) + Intel 3T (Base DIEs) + Intel 18A (chiplets) + Foveros Direct 3D + EMIB 3.5D + PowerVIA + RibbonFET (nanowires? nanosheets for Diamond Rapids?) + VcachePRO (Without Silicon Interposer like CoWoS-S) + FCBGA 2D+= 300 Billion Transistors.

Nvidia Blackwell = 208 Billion Transistors.

I think that Clearwater Forest is Best-In-Class in the industry. If Intel keeps what it promised (q4'2025), Intel is back. I have that idea, an idea CLEAR like WATER

 

[Wirko]

Foveros Direct 3D 9 microns bump pitch (vs 25 microns Foveros Omni) + EMIB = EMIB 3.5D

They really call it that! I read about 2.1D and 2.3D and 2.5D on Semianalysis, and didn't expect that the number of spatial dimensions would exceed 3 so soon.

 

[MiguelXTK]

"3.5D​

What is 3.5D? The simplest understanding is 3D+2.5D. However, since there is a new name, it must be supported by new technology. What is this new technology?

It is the Hybrid Bonding we talked about above.

Hybrid Bonding is applied to the direct interconnection of 3D TSVs, eliminating the need for bumps. Its interface interconnection spacing can be less than 10um or even 1um, and its interconnection density can reach 10,000~1,000,000 points per square millimeter.

This is far beyond the reach of traditional bump interconnections. Therefore, in high-density 3D interconnections, the bumps will eventually disappear, as shown in the figure below, which I have also explained in previous articles."

3D: Foveros Direct (9 microns copper-to-copper by thermocompression. Foveros Omni is now working, 2024, at 25 microns)
2.5D: EMIB 2.5D is now working (Sierra Forest 6 Xeon). If 2.5D is FCBGA + Si Interposer + DIEs (CoWoS-S), EMIB from Intel is 2.6D because eliminates 1 layer embedding silicon interposer into substrate.

And use Base DIE for "main cache" of 4 Chiplets is, in my opinion, another type of V-cache than AMD: Base Die: chiplet. Top die: cache.

Main cache in the base die of 4 chiplets is bigger (MB) than the cache of AMD X3D cache. And better in my opinion for thermal disipation (cpu top, sram botton). In AMD v-cache the SRAM top, CPU bottom covered with SRAM (hot).

We will see if InFO_POP works fine with the DRAM covering the CPU in A18 series.

 

[Prima.Vera]

Soon the CPUs will go back to the Pentium III era of hugeness: