AMD Launches New Slim Form Factor Alveo UL3422 Accelerator Card

[GFreeman]

AMD today announced the AMD Alveo UL3422 accelerator card, the latest addition to its record-breaking family of accelerators1 designed for ultra-low latency electronic trading applications. AMD Alveo UL3422 provides trading firms, market makers and financial institutions with a slim form factor accelerator optimized for rack space, cost and designed for a fast path to deployment in a wide range of servers. The Alveo UL3422 accelerator is powered by an AMD Virtex UltraScale+ FPGA that features a novel transceiver architecture with hardened, optimized network connectivity cores, custom built for high-speed trading. It enables ultra-low latency trade execution, achieving less than 3ns FPGA transceiver latency and breakthrough 'tick-to-trade' performance not achievable with standard off-the-shelf FPGAs.

"Speed is the ultimate advantage in the increasingly competitive world of high-speed trading," said Yousef Khalilollahi, corporate vice president & general manager, Adaptive Computing Group, AMD. "The Alveo UL3422 card provides a lower-cost entry point while still delivering cutting-edge latency performance, making it accessible to firms of all sizes that want to stay competitive in the ultra-low latency trading space."



New Slim Form Factor for Cost-Effective Deployment
The Alveo UL3422 accelerator card is packaged in a slim FHHL (full height, half length) form factor designed to fit into a wide range of servers and co-location exchange data centers.

Compared to its predecessor, the Alveo UL3422 accelerator reduces port density, on-board memory, and connectivity options, while still being powered by the same AMD Virtex UltraScale+ VU2P FPGA for ultra-low latency.

As a result, the Alveo UL3422 is half the size with equivalent performance to the existing Alveo UL3524 accelerator card which holds the current STAC-T0 benchmark world record for tick-to-trade performance. The slim FHHL form factor of the Alveo UL3422 allows financial institutions to cost-effectively optimize compute density and rack-space.

Ecosystem Solutions and Fast Path to Trade
The Alveo UL3422 accelerator card is designed for a fast path to deployment by utilizing available infrastructure ecosystem solutions and reference designs, giving trading developers the edge they need for rapid design closure and time to market.

It is supported by a growing network of ecosystem partner solutions that provide IP and development frameworks to enable the rapid implementation of trading solutions.

• Exegy, a provider of end-to-end, front-office trading solutions, is supporting the AMD Alveo UL3422 card with its Development Framework (nxFramework). nxFramework is a hardware and software development environment designed to efficiently build and maintain ultra-low latency FPGA applications for the financial industry.
• Hypertec, a provider of hardware, cloud, and value-added solutions for the financial services industry, has closely collaborated with AMD. The company's HF X410R-G6 server is certified to support the Alveo UL3422 accelerator, making it the first 1U server fully optimized for this card.
• Xelera Technologies, a software provider for high-speed network technology and machine learning (ML) applications, collaborated with AMD to help overcome the latency drawback of ML algorithms in high-frequency trading. With Xelera Silva users can take advantage of real-time, ML-based trading decisions while leveraging XGBoost, LightGBM, CatBoost and other advanced models.

The Alveo UL3422 supports traditional FPGA flows using the AMD Vivado Design Suite and comes with a suite of reference designs and performance benchmarks that allow FPGA designers to quickly explore key metrics and develop custom trading strategies to specification.

AMD is also providing developers with the open-sourced and community-supported FINN development framework, enabling low-latency AI models to be deployed into high-performance trading systems. FINN uses PyTorch and neural network quantization techniques designed to reduce the size of AI models while maintaining accuracy. The FINN compiler generates Quantized Neural Network (QNN) Hardware IP blocks that can be used with AMD FPGAs.

The AMD Alveo UL3422 accelerator card is currently available and shipping in production volumes to global financial services customers.



View at TechPowerUp Main Site | Source

 

[Dr. Dro]

Ah, I love the smell of post-merger and acquisition product launches. This is a Xilinx product through and through, you can see it even in the PR. They just did a search and replace on "Xilinx" with "AMD", doesn't even seem to be the same press team that works on it.

 

[natr0n]

I was like wtf is an accelerator card...? Then I see fpga which I know what that is Thanks @Dr. Dro

 

[JWNoctis]

So this is, technically, a DPU optimized for latency? Lots of players in that field there, but interesting.

I recall a tale, of some financial institution investing in some terrestrial microwave relay equipment in the 1960s, to get quotes a split-second earlier than over copper wire. This allowed them to shortcut competition, which turned out to be quite profitable. Guess this is the same idea here.

 

[Dr. Dro]

So this is, technically, a DPU optimized for latency? Lots of players in that field there, but interesting.

I recall a tale, of some financial institution investing in some terrestrial microwave relay equipment in the 1960s, to get quotes a split-second earlier than over copper wire. This allowed them to shortcut competition, which turned out to be quite profitable. Guess this is the same idea here.

Essentially, yes.

 

[Wirko]

So this is, technically, a DPU optimized for latency? Lots of players in that field there, but interesting.

I recall a tale, of some financial institution investing in some terrestrial microwave relay equipment in the 1960s, to get quotes a split-second earlier than over copper wire. This allowed them to shortcut competition, which turned out to be quite profitable. Guess this is the same idea here.

Half a century later the split-second became split-nanosecond, and the business based on that principle (HFT) became huge.

Ah, I love the smell of post-merger and acquisition product launches. This is a Xilinx product through and through, you can see it even in the PR. They just did a search and replace on "Xilinx" with "AMD", doesn't even seem to be the same press team that works on it.

It doesn't hurt that the logos are so similar. No one notices if they overlook some "X" logos during search and replace operation.

 

[AusWolf]

It's news like this that make me feel like I know nothing about tech. I have no idea what this thing is, or what it does.

 

[Patriot]

Ah, I love the smell of post-merger and acquisition product launches. This is a Xilinx product through and through, you can see it even in the PR. They just did a search and replace on "Xilinx" with "AMD", doesn't even seem to be the same press team that works on it.

The fact they are able to have a fpga based npu inside ryzen, and continue to push existing lines shows AMD did the acquisition correctly. They aren't suddenly bending the product lines that have existing customers to use AMD gpus. Intel....acquired Altera in 2015, and subsequently stalled for 2 generations letting Xilinx take the FPGA lead, now Intel is in the process of spinning off the company they killed.

 

[mkppo]

The fact they are able to have a fpga based npu inside ryzen, and continue to push existing lines shows AMD did the acquisition correctly. They aren't suddenly bending the product lines that have existing customers to use AMD gpus. Intel....acquired Altera in 2015, and subsequently stalled for 2 generations letting Xilinx take the FPGA lead, now Intel is in the process of spinning off the company they killed.

Yeah Intel really screwed up the Altera acquisition to the point where I forgot they even bought them.

Xilinx/AMD have been on a roll in recent times

 

[SOAREVERSOR]

It's news like this that make me feel like I know nothing about tech. I have no idea what this thing is, or what it does.

It's an FPGA (fully programable gate array) tuned for low latency. It's meant to be used alongside ML (machine learning) to help trade stocks faster as they change during the competition.

A ton of stuff on the stock market (or other trading markets) is not traded by humans. It's done by algorithms where the computer does all of it and being a nano second faster than your competitors can make billions. Being slower can cost billions. This is true to such an extent that firms place the machines that do this at exactly the right place on the existing fiber network to get their faster than another office. Except this one can work with a subset of AI known as ML which is used to create data models.

So it's basically there so your racks of servers can AI/ML create data models faster and get them to the market when things change faster, by nano seconds, than the competition so you can make money. As such it doesn't matter what it costs it will sell like crazy.

 

[Wirko]

The fact they are able to have a fpga based npu inside ryzen

Did they reveal anything like that? The closest thing I can find is "programmable interconnection" (which is the switching logic between AI tiles). It could be implemented as programmable logic similar to FPGA. I'm not sure it makes much sense.

 

[Dr. Dro]

The fact they are able to have a fpga based npu inside ryzen, and continue to push existing lines shows AMD did the acquisition correctly. They aren't suddenly bending the product lines that have existing customers to use AMD gpus. Intel....acquired Altera in 2015, and subsequently stalled for 2 generations letting Xilinx take the FPGA lead, now Intel is in the process of spinning off the company they killed.

Yeah. The progress with Ryzen has been nothing short of amazing, and AMD's modular architecture really helped here. Once openSIL rolls out and the usually secretive functionality of AGESA becomes open-source, we're going to see some of the best improvements we've ever seen in the CPU front, not that we already aren't. The future is both bright and exciting.

 

[AusWolf]

It's an FPGA (fully programable gate array) tuned for low latency. It's meant to be used alongside ML (machine learning) to help trade stocks faster as they change during the competition.

A ton of stuff on the stock market (or other trading markets) is not traded by humans. It's done by algorithms where the computer does all of it and being a nano second faster than your competitors can make billions. Being slower can cost billions. This is true to such an extent that firms place the machines that do this at exactly the right place on the existing fiber network to get their faster than another office. Except this one can work with a subset of AI known as ML which is used to create data models.

So it's basically there so your racks of servers can AI/ML create data models faster and get them to the market when things change faster, by nano seconds, than the competition so you can make money. As such it doesn't matter what it costs it will sell like crazy.

Aha... So it's an AI bot designed to trade stocks over an ultrafast network. It'd be nice to know how it works, and what those weird-looking ports are on it, but I guess that's a story for another day.

 

[Wirko]

Aha... So it's an AI bot designed to trade stocks over an ultrafast network. It'd be nice to know how it works, and what those weird-looking ports are on it, but I guess that's a story for another day.

Somehow, banknote-sized paper and green ink go in at the right, and the result flies out at the left, as fast as you can feed the paper.