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As a quick follow-up to last week's "Arrow Lake-S" de-lidding by Madness727, we now have a line-up of a de-lidded Core Ultra 9 285K "Arrow Lake-S" processor placed next to a Core i9-14900K "Raptor Lake-S," and the Core i9-12900K "Alder Lake-S." The tile-based "Arrow Lake-S" is visibly larger than the two, despite being made on more advanced foundry nodes. Both the 8P+16E "Raptor Lake-S" and 8P+8E "Alder Lake-S" chips are built on the Intel 7 node (10 nm Enhanced SuperFin). The "Raptor Lake-S" monolithic chip comes with a die-area of 257 mm². The "Alder Lake-S" is physically smaller, at 215 mm². What sets the two apart isn't just the two additional E-core clusters on "Raptor Lake-S," but also larger caches—2 MB of L2 per P-core, increased form 1.25 MB/core, and 4 MB per E-core cluster, increased from 2 MB/cluster.
Thanks to high quality die-shots of the "Arrow Lake-S" by Madness727, we have our first die-area estimations by A Hollow Knight on Twitter. The LGA1851 fiberglass substrate has the same dimensions as the LGA1700 substrate. This is to ensure the socket retains cooler compatibility. Using geometrical measurements, the base tile of the "Arrow Lake-S" is estimated to be 300.9 mm² in area. The base-tile is a more suitable guideline for "die-area," since Intel uses filler tiles to ensure gaps in the arrangement of logic tiles are filled, and the chip aligns with the base-tile below. The base tile, built on an Intel 22 nm foundry node, serves like a silicon interposer, facilitating high-density microscopic wiring between the various logic tiles stacked on top, and an interface to the fiberglass substrate below.
A Hollow Knight also put out his die-area estimations for each of the individual tiles. The Compute tile is estimated to measure 114.5 mm². This is the largest tile by area, and is built on the 3 nm TSMC N3B foundry node, and contains the CPU core complex with an 8P+16E core-count. The second-largest tile is the SoC tile, estimated to measure 86.1 mm². This tile is built on the 6 nm TSMC N6 node. The I/O tile is an extension of the SoC tile, it is built on the same 6 nm node, and is estimated to measure 23.79 mm².
The Graphics tile is, interestingly, smaller than even the I/O tile, and measures 22.8 mm². Intel built this on the 5 nm TSMC N5 node. It contains the brains of the iGPU, with 4 Xe cores, and other graphics rendering machinery. The media-accelerators, display controller, and display PHY components, are located on the SoC tile. Then there are the two filler tiles, the more visible of the two is the one next to the I/O tile, measuring 17 mm², and a smaller one next to the Graphics tile, measuring 2.6 mm². The filler tiles ensure the clump of logic tiles ends up having a rectangular form and a uniform Z-Height.
Interestingly, a slender, rectangular portion of the base tile remains exposed, with nothing stacked on top. This is what contributes to the 300.9 mm² die-area measurement by A Hollow Knight. If you were to simply add up the areas of the logic tiles, subtracting this exposed portion of the base tile, and the two filler tiles, you end up with 247.2 mm², which is in fact smaller than that of the monolithic "Raptor Lake-S."
View at TechPowerUp Main Site | Source
Thanks to high quality die-shots of the "Arrow Lake-S" by Madness727, we have our first die-area estimations by A Hollow Knight on Twitter. The LGA1851 fiberglass substrate has the same dimensions as the LGA1700 substrate. This is to ensure the socket retains cooler compatibility. Using geometrical measurements, the base tile of the "Arrow Lake-S" is estimated to be 300.9 mm² in area. The base-tile is a more suitable guideline for "die-area," since Intel uses filler tiles to ensure gaps in the arrangement of logic tiles are filled, and the chip aligns with the base-tile below. The base tile, built on an Intel 22 nm foundry node, serves like a silicon interposer, facilitating high-density microscopic wiring between the various logic tiles stacked on top, and an interface to the fiberglass substrate below.
A Hollow Knight also put out his die-area estimations for each of the individual tiles. The Compute tile is estimated to measure 114.5 mm². This is the largest tile by area, and is built on the 3 nm TSMC N3B foundry node, and contains the CPU core complex with an 8P+16E core-count. The second-largest tile is the SoC tile, estimated to measure 86.1 mm². This tile is built on the 6 nm TSMC N6 node. The I/O tile is an extension of the SoC tile, it is built on the same 6 nm node, and is estimated to measure 23.79 mm².
The Graphics tile is, interestingly, smaller than even the I/O tile, and measures 22.8 mm². Intel built this on the 5 nm TSMC N5 node. It contains the brains of the iGPU, with 4 Xe cores, and other graphics rendering machinery. The media-accelerators, display controller, and display PHY components, are located on the SoC tile. Then there are the two filler tiles, the more visible of the two is the one next to the I/O tile, measuring 17 mm², and a smaller one next to the Graphics tile, measuring 2.6 mm². The filler tiles ensure the clump of logic tiles ends up having a rectangular form and a uniform Z-Height.
Interestingly, a slender, rectangular portion of the base tile remains exposed, with nothing stacked on top. This is what contributes to the 300.9 mm² die-area measurement by A Hollow Knight. If you were to simply add up the areas of the logic tiles, subtracting this exposed portion of the base tile, and the two filler tiles, you end up with 247.2 mm², which is in fact smaller than that of the monolithic "Raptor Lake-S."
View at TechPowerUp Main Site | Source
