AMD "Zen 6" to Retain Socket AM5 for Desktops, 2026-27 Product Launches

[Wirko]

AMD was strict about X870(E) having USB4 support. ASMedia USB4 controller (ASM4242) consumes four PCIe Gen 4.0/5.0 lanes (two per USB4 port). There was really no other choice for mobo makers but to implement it CPU-wise, since it could not be possible chipset-wise. So AMD was not so strict, but there was no other choice.

AMD demands that the USB4 controller be connected to the CPU, no the chipset. But they obviously allowed a deviation that MSI implemented. It looks like some dirty trick without a PCIe switch. But whatever it is, other manufacturers could do that too.

Agree, but I think it's vital for AMD to finally introduce more cores per CCD with AM5 and not wait for AM6.

To me, a logical solution would be to design two different chiplets with a different number of big cores. 6 and 12, for example. AMD thinks otherwise, it seems.

Assuming Intel exists in 2027 as an x86 CPU designer.

At the very least, Intel will be a neutron star, after having absorbed all the heavy dollars and collapsing into a two-room office.

 

[SL2]

I'm not sure launching new CPU types close to every year makes sense, it's been a while since AMD did that.

Zen+: 399 days since last launch.
Zen2: 445
Zen3: 488
Zen4 691
Zen5 682

 

[windwhirl]

To me, a logical solution would be to design two different chiplets with a different number of big cores. 6 and 12, for example. AMD thinks otherwise, it seems.

My guess is that 8-core CCDs give AMD enough flexibility. The ones with failed cores can be used to populate the 6-core Ryzen SKUs (or even 4-core ones, if there are any still there), the ones with no failed cores can go for the 8-core SKUs. And with that, you can also make 12 and 16 core SKUs.

All the engineering time is spent on a single design, no need to re-do parts of the design just to add or substract cores from the original design.

 

[Zach_01]

AMD MUST to abandon the old idea of putting the memory controller (IMC) on the IO die and start putting it on the same die as the x86 cores to the latency of accessing the main RAM be the lowest possible.

Example:

Cant happen... or better... no they wont do this move.
If AMD do this, they will have to abandon the universal CCD/CCX that now fits all of their platforms. The exact same CCD/CCX that fits CPUs from <$300 up to $10,000+. From 6/8 cores up to 128.
Can you understand the convenience and cost reduction that this provides? Along with the avoidance of complexity of TSMC wafer allocation and distribution between platforms, if several different designs were to exist. AMD does not need this kind of a headache.
Your way of thinking is too narrow(?) and PC oriented without considering(?) that the big game is on EPYC. What we get as PC end users (even threadripper) is the low-end by-product of that game.
Feet on the ground and facing the facts

On the other hand they do need a faster (high frequency) UMC and IF/DF as 9000 has shown. Probably (most likely) this will drive overall CPU package power up, so that will require also a much better node for SoC and CCD/CCX to compensate.
Soon to come I believe

 

[kapone32]

Cant happen... or better... no they wont do this move.
If AMD do this, they will have to abandon the universal CCD/CCX that now fits all of their platforms. The exact same CCD/CCX that fits CPUs from <$300 up to $10,000+. From 6/8 cores up to 128.
Can you understand the convenience and cost reduction that this provides? Along with the avoidance of complexity of TSMC wafer allocation and distribution between platforms, if several different designs were to exist. AMD does not need this kind of a headache.
Your way of thinking is too narrow(?) and PC oriented without considering(?) that the big game is on EPYC. What we get as PC end users (even threadripper) is the low-end by-product of that game.
Feet on the ground and facing the facts

On the other hand they do need a faster (high frequency) UMC and IF/DF as 9000 has shown. Probably (most likely) this will drive overall CPU package power up, so that will require also a much better node for SoC and CCD/CCX to compensate.
Soon to come I believe

AMD APUs are masters at RAM OC.

 

[Wirko]

My guess is that 8-core CCDs give AMD enough flexibility. The ones with failed cores can be used to populate the 6-core Ryzen SKUs (or even 4-core ones, if there are any still there), the ones with no failed cores can go for the 8-core SKUs. And with that, you can also make 12 and 16 core SKUs.

All the engineering time is spent on a single design, no need to re-do parts of the design just to add or substract cores from the original design.

The flexibility is certainly there, and we shall not forget the Epycs with just one active core, but full 32MB L3, on each CCD. I don't know this part of market but AMD may be selling those in considerable numbers.

 

[Zach_01]

AMD APUs are masters at RAM OC.

No doubt, and they need the larger bandwidth and the lower latency.
I bet these monolithic bigger designs have much lower fab yields. More expensive.
I expect the next gen AMD APUs with those huge graphics to be super expensive.

 

[Nhonho]

Cant happen... or better... no they wont do this move.
If AMD do this, they will have to abandon the universal CCD/CCX that now fits all of their platforms. The exact same CCD/CCX that fits CPUs from <$300 up to $10,000+. From 6/8 cores up to 128.
Can you understand the convenience and cost reduction that this provides? Along with the avoidance of complexity of TSMC wafer allocation and distribution between platforms, if several different designs were to exist. AMD does not need this kind of a headache.
Your way of thinking is too narrow(?) and PC oriented without considering(?) that the big game is on EPYC. What we get as PC end users (even threadripper) is the low-end by-product of that game.
Feet on the ground and facing the facts

On the other hand they do need a faster (high frequency) UMC and IF/DF as 9000 has shown. Probably (most likely) this will drive overall CPU package power up, so that will require also a much better node for SoC and CCD/CCX to compensate.
Soon to come I believe

CCD/CCX are not universal. In the ZEN5 generation, there are 4 different CCD/CCX, in addition to the APUs, which are single-die. And also the IO die of consumer and server CPUs are different. You have naive notions.

Yes, EPYC CPUs are where most of the money is, but AMD makes a lot of money selling desktop CPUs.

Placing the memory controller on the same die as the x86 cores would be a very quick, simple and easy way (during the design phase) to increase the IPC of the x86 cores, since they would have much faster access to the main RAM. And perhaps the cost of manufacturing the processor would be cheaper because, with the memory controller (IMC) on the same die as the x86 cores, it would not need to have such a large amount of L3 cache memory. AMD wouldn't need to increase the usual amount of L3 (32 MB) on its "non-3D cache" CPUs. And even on the 3D-cache CPUs, it could only put 32 MB more L3 instead of 64 MB, since CPUs with IMC on the same die as the x86 cores don't need that much cache memory.

 

[Count von Schwalbe]

CCD/CCX are not universal. In the ZEN5 generation, there are 4 different CCD/CCX, in addition to the APUs, which are single-die. And also the IO die of consumer and server CPUs are different. You have naive notions.

2. Or one if you count Zen 5c as a separate gen.

The 6 vs 8 core chiplet are the same silicon, as are the X3D variants of same. They are picked over for yields, which is where the variations come in. The X3D chiplet is separate silicon added later. You might say they are all different vehicles based on the same chassis.

The full-fat Zen 5 EPYC use the same CCD as consumer parts, only the IOD and substrate are different.

Placing the memory controller on the same die as the x86 cores would be a very quick, simple and easy way (during the design phase) to increase the IPC of the x86 cores, since they would have much faster access to the main RAM. And perhaps the cost of manufacturing the processor would be cheaper because, with the memory controller (IMC) on the same die as the x86 cores, it would not need to have such a large amount of L3 cache memory. AMD wouldn't need to increase the usual amount of L3 (32 MB) on its "non-3D cache" CPUs. And even on the 3D-cache CPUs, it could only put 32 MB more L3 instead of 64 MB, since CPUs with IMC on the same die as the x86 cores don't need that much cache memory.

They did that once, with Zen and Zen+. They moved away from that idea for a reason.

Look at the current lineup of chiplet CPUs. They range from 6 or 8 cores on one die to 12 or 16 on 2 dice. To pair a single IMC with dual-channel memory with that combination you have a dilemma.

Option 1: split it in half, one IMC per chiplet. That gives you a latency penalty if you need to access Channel 2 from Chiplet 1 (same as existing) on 12 and 16 core models, so the benefit would be hit and miss. Also, you would limit 6 and 8 core models to single channel memory, and I doubt people would accept that limitations.

Option 2: double up. One full dual-channel IMC per CCD. You just made Threadripper with quad-channel memory. They are expensive for a reason, even the 12 and 16 core models. I doubt they could be compatible with standard AM5 with its dual-channel interface.

Option 3a: big CCD. Make the CCD 16 cores and chop it down for lesser models. Not economically viable for anything smaller than 12 cores. Probably not even that.

Option 3b: multiple sizes of CCD. Make 3-4 CCD sizes with its own IMC. You just reinvented monolithic chips. There is a reason AMD is making CCDs, and Intel is moving to that model. The APUs are all relatively small chips, which helps keep them relatively low cost.

Nope, the current light latency penalty is worth it, it is what is getting us 16 core gaming monsters for the relatively low prices we have.

 

[Raiden85]

Well, that was going to be pretty damn obvious when you have about 2 to 3 years left on this socket. This isn’t Intel.

Considering how long is left, there should even be a chance of seeing Zen 7 on AM5 as well.

 

[Zach_01]

CCD/CCX are not universal. In the ZEN5 generation, there are 4 different CCD/CCX, in addition to the APUs, which are single-die. And also the IO die of consumer and server CPUs are different. You have naive notions.

Yes, EPYC CPUs are where most of the money is, but AMD makes a lot of money selling desktop CPUs.

Placing the memory controller on the same die as the x86 cores would be a very quick, simple and easy way (during the design phase) to increase the IPC of the x86 cores, since they would have much faster access to the main RAM. And perhaps the cost of manufacturing the processor would be cheaper because, with the memory controller (IMC) on the same die as the x86 cores, it would not need to have such a large amount of L3 cache memory. AMD wouldn't need to increase the usual amount of L3 (32 MB) on its "non-3D cache" CPUs. And even on the 3D-cache CPUs, it could only put 32 MB more L3 instead of 64 MB, since CPUs with IMC on the same die as the x86 cores don't need that much cache memory.

You keep reiterating the same again and again because that suits your narrative. And I have naive notions. Ok!
Yes CCD/CCX is universal from a 6core R5 7500 up to the 128core EPYCs.

Leave APUs, ZenC and I/O dies out. Those dies are created to serve different needs. And your suggestion for AMD is to have even more different dies because you are stuck in the old monolithic design.
We all know that monolithic designs are faster, but also expensive because of much lower yields.
AMD is trying to keep dies as small as possible and you would like to get them bigger and bigger for the sake of latency?

AMD CPU engineers are so incompetent...

 

[A Computer Guy]

And AM4 will probably get something else from the garbage bin

I'm still holding out hope for a nostalgic Overdrive CPU like a Zen4/5 that works in AM4 socket.

 

[Nhonho]

You are stuck with old ideas and think that AMD engineers are incapable of putting the memory controller on the same die as the x86 cores. The chiplets that would be connected to the main die could have more cache (50 MB of L3 cache, for example) to compensate the higher latency of accessing the main RAM, while the main die with the integrated memory controller could continue with 32 MB of L3 cache.

 

[qcmadness]

AMD ditched on-ccx memory controllers because it is not compelling in server market where you need NUMA support which is very troublesome.

 

[SL2]

AMD ditched on-ccx memory controllers because it is not compelling in server market where you need NUMA support which is very troublesome.

Speaking of old ideas: NUMA.

Thanks for reminding me. I highly doubt it would work any better on desktop.

 

[StimpsonJCat]

AMD MUST to abandon the old idea of putting the memory controller (IMC) on the IO die and start putting it on the same die as the x86 cores to the latency of accessing the main RAM be the lowest possible.

Example:

Or put a large 128MB L4 cache on the I0 die and reduce the size of the L3 cache on the CPU...

 

[Space Lynx]

this is excellent news, I will def upgrade to 11800x3d then

 

[kapone32]

AM3 was like this. AM4 was an example of why you do this. AM5 (if the prices of parts relax) could be the Phoenix that is represented in the nomenclature. People are going to get even faster CPUs and GPUs than we have today and you won't have to change your MB, Storage array, Cooling setup or Game files. In most cases even OS (I would still refresh though). I was pumped about the 9900X3D but unless that chip has double the Cache available as a pool to both CCDs I don't see it being faster in non X3D chips than 7000 but we will see. The CPU Wars have been popcorn inducing with the narrative trying to fit AMD Square box in Intel's Circle until the box expanded to include the circle.

I am going to keep arguing this as well. Yes Intel still has market share but AMD owns innovation in the CPU space. As such they have made the traditional way of reviewing CPUs inert at some level. Here is what I mean. Is the 8700G faster than a 7700X for IGPU Gaming? Is a 7800X3D slower than a 7700x in CPU intensive Games? Those are known factors now. So when the 7700X could not best the 5800X3D in Vcache Games did it make it slower in everything else? It is the 8700G review. There should be no DGPU numbers in IGPU tests, Especially now that we have a form factor on PC that relies on IGPU. Of course no one is going to listen because the narrative is so strong that this thread was made for a truth that has been with us for more than 15 years.

 

[R0H1T]

You are stuck with old ideas and think that AMD engineers are incapable of putting the memory controller on the same die as the x86 cores. The chiplets that would be connected to the main die could have more cache (50 MB of L3 cache, for example) to compensate the higher latency of accessing the main RAM, while the main die with the integrated memory controller could continue with 32 MB of L3 cache.

Wait so you think it should be made like this? Is that supposed to be with IMC on the same (compute) die

 

[TechLurker]

And AM4 will probably get something else from the garbage bin

Finally, the 5950X3D with under-die cache! The grand finale for AM4, thanks to culmination of advancements in AM5! Faster than the legendary 5800X3D, and overclockable unlike the other AM4 X3Ds! /humor

 

[Count von Schwalbe]

I wonder if the IMC could be put on a stack die like the cache of an X3D.

It won't make sense to integrate it with the actual chiplet silicon, but stacking it would have a lower latency penalty vs IF.

And you could add cache to the second die to buffer that compute cluster with its higher RAM latency.

 

[Tigerfox]

If AMD really wants for AM5 to live till the end of 2027, with release of Zen 6 they really should:
- make a proper IOD, add native support for CUDIMMS and higher clocks, decrease DDR5 latencies, significantly improve memory controller bandwidth;

I don't really know if Ryzen will profit as much from faster memory. Isn't it a good thing AMD isn't ad memory sensitive as Intel?

- upgrade CPU <> chipset interconnection to PCIe Gen 5 x4;

I fully agree. They could use 4 additional lanes from the CPU for Gen4x8 or Gen5x8, but that would limit available lanes even more-

- make USB 4.0 support chipset-bound, don't hang it onto CPU lanes and stop crippling CPU-bound PCIe lanes;

No, put USB4 into the IOD. It already is in Phoenix/Hawk Point and Strix Point. Sadly, only one B650E mainboard from Gigabyte supports using USB4 from CPU.

- add at least 2 more cores per CCD while retaining similar CCD TDP to 8 cores per CCD;

I don't think you just add 2 Cores, you probably only can double core count to 16.

- bring back PCIe ports, since they are versatile, specify for motherboard makers to have more than just two expansion slots (1x PCIe 5.0 x16 + 2x PCIe 4.0 x4 + 1x PCIe 4.0 x 4 is ideal);

You mean offer more PCIe lanes so motherboard makers are able to offe more PCIe-slots. AMD can't force them to put those lanes into PCIe-slots. That being said, sadly, M.2 and gigantic GPU-coolers are killing space for PCIe-slots.

- lower native SATA ports, 2 are enough, I'd even prefer motherboards with no SATA support at all (PCIe ports can be converted into SATA ports with adaptor).

- Dissagree, I want 6xSATA back.

AM3 was like this.

Not exactly. AM3 was PhenomII only, so you really could only use one or let's 1 and 1/2 gens. It started with Phenom II X4 955 BE, which got to 980 over the years with a better stepping, and latter addes sixcore PhenomII X6 1090T and 1100T BE. That's it, all 45nm, all the same tech, just more clock (+500MHz) and more cores. Everything else you could put in there ware slower, had less cores and cache or was older. Allthough you could put all those CPU into AM2+, too.

For Bulldozer, you needed AM3+. There were new revisions of old AM3-boards, looking the same, except the colour of the socket, put you couldn't plug a Bulldozer-CPU into an pre-Bulldozer AM3-board. 970/990X/990FX-chipset was the same as 870/790F/890FX.

AM2 had a long life only in theory, too. With the right board, like many Asus and Gigabyte, you could upgrade from Athlon64 90nm F2-Stepping to PhenomII X4 45nm up to 95W (meaning 945 or 955 non BE). In reality, most board never got the needed BIOS-update, some boards from cheap manufacturers like ECS and Biostar didn't even get Athlon64 in 65nm.

But with the right Board, you could upgrade your P965- or i975X-board from the first 65nm Core 2 Duo "Conroe" up to the latest 45nm Core 2 Quad "Yorkfield" and stay superior to AMD the whole AM2, AM2+ and AM3-era. With the wrong board from the wrong manufacturer or with a nForce-chipset, you had to change board for FSB1333 and again for 45nm.

I made the mistake and bought a Abit KN9 Ultra with nForce 570 Ultra in fall of 2006. It never got a Phenom-BIOS because Abit went out of business, so I only got to Athlon64 X2 5400+ BE. Furthermore, it was a bad overclocker, so I only got my X2 3800+ to 2,7GHz instead of ~3GHz and my 5400+ to just 3,1GHz, but as a poor student, it had to soldier on until I got a Z87-board with 5670K in 2013.

Had I bought a Asus M2N-E or Gigabyte GA-M57SLI-(D)S4, I would have been able to upgrade to PhenomII X4 955. Or would I have bought an ASUS P965 (which would have been more expensive), I would have been able to upgrade to Core 2 Quad 9650 and OC that.

 

[Count von Schwalbe]

I don't think you just add 2 Cores, you probably only can double core count to 16.

On a new uArch it is certainly possible.

I personally would like to see stuff drop down the stack a level;
R3 6-core
R5 8-core
R7 12-core
R9 16-core
R9.5 8 Zen 6 cores + 16 Zen 6c cores. Unfortunately I think the 6c cores will be 32-core chiplets, so that is extremely unlikely. Perhaps using defective CCDs if EPYC doesn't take them all.

 

[Zach_01]

I don't really know if Ryzen will profit as much from faster memory. Isn't it a good thing AMD isn't ad memory sensitive as Intel?

True^^
Primarily what next gen Ryzen needs desperately is faster data CCD-IOD interconnection, AKA higher InfinityFabric (FCLK) speed and maybe UMC (UCLK) speed also.
A better I/O Die all together.
Then we can talk about faster memory (8000~10000MT/s)
Current configurations (Zen5) cant be benefited much even with 10000MT/s.

X3Ds are bypassing (in a way) the FCLK, UCLK bottleneck with the extra cache connected directly to core CCD.

Maybe AMD is waiting until it gets to 2-4nm nodes for CCD/IOD because with the current 4/6nm its not possible to raise FCLK and UCLK without making the CPU package really power hungry.
Its the trade-off of any modular design. High yields, low cost but high-er power. Same story with RDNA3.
Dont get me wrong, the CPU IOD alone does not draw much power. But adding FCLK power on top it can be a substantial amount out of total package power (PPT).
Users of desktop 3000 up to 9000series who use HWiNFO64 and actually observe power metrics, know this first hand.

 

[kapone32]

True^^
Primarily what next gen Ryzen needs desperately is faster data CCD-IOD interconnection, AKA higher InfinityFabric (FCLK) speed and maybe UMC (UCLK) speed also.
A better I/O Die all together.
Then we can talk about faster memory (8000~10000MT/s)
Current configurations (Zen5) cant be benefited much even with 10000MT/s.

X3Ds are bypassing (in a way) the FCLK, UCLK bottleneck with the extra cache connected directly to core CCD.

Maybe AMD is waiting until it gets to 2-4nm nodes for CCD/IOD because with the current 4/6nm its not possible to raise FCLK and UCLK without making the CPU package really power hungry.
Its the trade-off of any modular design. High yields, low cost but high-er power. Same story with RDNA3.
Dont get me wrong, the CPU IOD alone does not draw much power. But adding FCLK power on top it can be a substantial amount out of total package power (PPT).
Users of desktop 3000 up to 9000series who use HWiNFO64 and actually observe power metrics, know this first hand.

Don't forget that from 7000 they have also added an IGPU. I don't know for sure what is happening but I also see that in use in some Games as well. It might even be a CCD limitation as the APUs have no problem responding and supporting faster memory.