Samsung's Second-Gen 3 nm GAA Process Shows 20% Yields, Missing Production Goals

[AleksandarK]

Samsung's latest semiconductor manufacturing technology is falling short of expectations, as the company struggles to achieve acceptable production rates for its cutting-edge 3 nm chips. The latest rumors indicate that both versions of Samsung's 3 nm Gate-All-Around (GAA) process produce fewer viable chips than anticipated. The initial targets set by the South Korean tech giant were aimed at a 70% yield rate in volume production. However, the first "SF3E-3GAE" iteration of the technology has only managed to achieve between 50-60% viable yield output. More troubling is the performance of the second-generation process, which is reportedly yielding only 20% of usable chips—a figure that falls dramatically short of production goals. The timing is particularly challenging for Samsung as major clients begin to reevaluate their manufacturing partnerships.

Qualcomm has opted to produce its latest Snapdragon 8 Elite processors exclusively through rival TSMC's 3 nm facilities. Even more telling is the exodus of South Korean companies, traditionally loyal to Samsung, who are now turning to TSMC's more reliable manufacturing processes. While Samsung can claim the achievement of bringing 3 nm GAA technology to market before TSMC's competing N3B process, this technical victory rings hollow without the ability to mass-produce chips efficiently. The gap between Samsung's aspirations and manufacturing reality continues to widen. However, Samsung is shifting its focus toward its next technological milestone. Development efforts are reportedly intensifying around a 2 nm manufacturing process, with plans to debut this technology in a new Exynos processor (codenamed 'Ulysses') for the 2027 Galaxy S27 smartphone series.



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[Assimilator]

Protip for Samsung: a second-generation is supposed to be better than the previous gen, not worse. 20% yield is... ouch.

 

[Bwaze]

"However, Samsung is shifting its focus toward its next technological milestone. Development efforts are reportedly intensifying around a 2 nm manufacturing process, with plans to debut this technology in a new Exynos processor (codenamed 'Ulysses') for the 2027 Galaxy S27 smartphone series."

If we can't make this process work, let's just jump to the next one, even harder to make? What could possibly go wrong?

I think TSMC will soon find they can charge much more for their products, since there will be no competition at the top...

 

[TumbleGeorge]

60% viable yield output

Not too bad.

 

[Daven]

I think process shrinks are starting to slow down again. Samsung is having problems at 3 nm (forget what they say about 2 nm), Intel is having problems going below 3 nm (20A is cancelled and forget about 18A) and TSMC has just barely started with its 3 nm node (2 nm not due for years). Even though all three share the same node name, they couldn't be more different with TSMC's 3 nm node taking the performance crown. Intel and Samsung are about the same. We might be at 3 nm from all three companies for a while.

 

[Eternit]

I think process shrinks are starting to slow down again. Samsung is having problems at 3 nm (forget what they say about 2 nm), Intel is having problems going below 3 nm (20A is cancelled and forget about 18A) and TSMC has just barely started with its 3 nm node (2 nm not due for years). Even though all three share the same node name, they couldn't be more different with TSMC's 3 nm node taking the performance crown. Intel and Samsung are about the same. We might be at 3 nm from all three companies for a while.

Samsung 3nm and 3nm gen 2 are similar to Intel 20A and 18A. Intel 20A/18A used to be named 5nm/5nm+. TSMC N3 doesn't use GAA so it was easier to implement, but they won't be able to progress further without GAA.

 

[Tomorrow]

Not too bad.

Essentially throwing away over 1/3rd of your production volume? I would call this pretty bad. 60% is barely viable for mass production.
Up to 50% is risk production. Up to 75% is ramp-up and over 85% are mature yields.

TSMC has historically had 70%+ even in the risk-production phase. Their initial 3nm was the exception with 55% but N3E has improved this to over 70%.
Samsung's 20% for risk-production or 60% for ramp-up are pretty abysmal in comparison.
Im guessing Intel 20A was equally as bad which is why it was canned.

 

[bonehead123]

Sounds like Samsung is saying:

"Hey Uncle Sam, how about giving us a few billions of dat fat CHIPS money, so we can fix this" ?

 

[Daven]

Sounds like Samsung is saying:

"Hey Uncle Sam, how about giving us a few billions of dat fat CHIPS money, so we can fix this" ?

They have to commit to building a fab in America for that to work.

 

[R0H1T]

60% is barely viable for mass production.

That also depends on your die size, this is probably one of those trial runs for big(?) chips.

AMD could probably make this work with their chiplets, even Intel for their consumer lineup if it's performant.

 

[Darc Requiem]

Why does Samsung keep going to the next node when they can't get their current node right? Didn't they do this with 5nm too?

 

[Eternit]

Why does Samsung keep going to the next node when they can't get their current node right? Didn't they doe this with 5nm too?

Intel is doing the same.

 

[TheinsanegamerN]

That also depends on your die size, this is probably one of those trial runs for big(?) chips.

AMD could probably make this work with their chiplets, even Intel for their consumer lineup if it's performant.

You dont do trial runs on big chips, you start with smaller, cheaper designs. think phone CPUs. Not big bois. This is why apple's A series are usually the first on a new TSMC design.

Those chiplets would cost an arm and a leg with 60% yield.

 

[Wirko]

Essentially throwing away over 1/3rd of your production volume? I would call this pretty bad. 60% is barely viable for mass production.
Up to 50% is risk production. Up to 75% is ramp-up and over 85% are mature yields.

TSMC has historically had 70%+ even in the risk-production phase. Their initial 3nm was the exception with 55% but N3E has improved this to over 70%.
Samsung's 20% for risk-production or 60% for ramp-up are pretty abysmal in comparison.
Im guessing Intel 20A was equally as bad which is why it was canned.

Realistically, we might be near te end of the road. Technology will still be able to find the (slow) road ahead. Economics, maybe not. Cost per transistor has the potential to keep decreasing *if* the volume of manufactured chips keeps growing exponentially. That will be hard.

 

[AnotherReader]

You dont do trial runs on big chips, you start with smaller, cheaper designs. think phone CPUs. Not big bois. This is why apple's A series are usually the first on a new TSMC design.

Those chiplets would cost an arm and a leg with 60% yield.

AMD's chiplets are significantly smaller than Apple's smartphone SOCs.

 

[wawa]

Looks like good news to me. 60% yield for 3nm GAA is a noticeable improvement. The fact they are the only one putting GAA technology to work at that yield is good news. Interesting..

 

[Count von Schwalbe]

You dont do trial runs on big chips, you start with smaller, cheaper designs. think phone CPUs. Not big bois. This is why apple's A series are usually the first on a new TSMC design.

Those chiplets would cost an arm and a leg with 60% yield.

300mm wafer is 942.5mm2, maybe 900mm2 usable as they are circular.

Apple a18 is 90mm2 and the Pro model is 105mm2.

Zen 5 Chiplet is 70mm2.

I would also think the chiplets could absorb a higher defect rate, with the ability to disable up to 2 cores.

 

[TumbleGeorge]

300mm wafer is 942.5mm2

S=π r²
3.14*150²= ~70650mm²

 

[R0H1T]

So 300mm is radius or diameter?

Those chiplets would cost an arm and a leg with 60% yield.

Pretty sure no one's doing smaller chips/chiplets than AMD among the top players!

 

[Count von Schwalbe]

S=π r²
3.14*150²= ~70650mm²

You're right, I hit the wrong button on my calculator

 

[kondamin]

So 300mm is radius or diameter?


Pretty sure no one's doing smaller chips/chiplets than AMD among the top players!

How big is the soc used in the apple Watch or in any of the smart wear stuff?

 

[R0H1T]

We're talking about general purpose chips, if we're going down that route then something like the PSP on AMD chips could be even smaller. Anyway the point still remains that chiplets should do better than monolithic dies.

 

[Eternit]

How big is the soc used in the apple Watch or in any of the smart wear stuff?

But the latest SoC from Series 10 is manufactured in TSMC N4P up to Series 8 they were manufactured in N7P while M3 and A17 have been manufactured in N3B for more than a year.

 

[x4it3n]

 

[Prima.Vera]

Maybe the ASML tools are not that good anymore, if all 3 manufacturers have big issues with the process...