Intel 0x114 Microcode Could be the Magic Gaming Performance Fix for "Arrow Lake"

[btarunr]

The gaming performance of Intel's latest Core Ultra 200-series "Arrow Lake-S" desktop processors missed the mark by quite a bit, ending up slower than the 14th Gen Core "Raptor Lake" processors. Adding pressure to Intel is AMD's recent launch of the Ryzen 7 9800X3D, which extends the company's leadership in gaming performance, ending up to 12% faster than the top Core Ultra 9 285K at gaming (1080p). The company then announced that it has identified possible reasons why gaming performance of "Arrow Lake" ended up below expectations, and that it's working on a microcode-level update to the processor.

A discussion in the ASUS ROG Forums sheds light on what this microcode update could be. Allegedly, it's called the Intel 0x114 Microcode Update, and you can expect it soon in a beta UEFI firmware update from ASUS and other motherboard vendors, which makes it possible that we see a public release of the microcode either by yearend, or in Q1-2025. There's still no word on the extent of gaming performance gain from this microcode, but if we were to speculate, Intel wouldn't bother with such an update if it didn't at least bring "Arrow Lake" to the same gaming performance level as "Raptor Lake," if not higher.



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[matar]

Doesn't intel have game testers to test their CPU before release if they want to hire me, I can do that just send me the hardware and i will test them12 hours a day.

 

[nguyen]

I sure the handful of people who bought Intel 15th gen CPU will be happy

 

[umeng2002]

A wunderwaffe won't save these CPUs.

 

[usiname]

There's still no word on the extent of gaming performance gain from this microcode, but if we were to speculate, Intel wouldn't bother with such an update if it didn't at least bring "Arrow Lake" to the same gaming performance level as "Raptor Lake," if not higher.

The fact that they don't mention gaming performance improvement mean less than raptor lake. They already lied that both are within the margin of error. They can't lie again and get ugly reviews for second time that expose their lies

 

[AcE]

This will probably not change much in the grand scape. Plus X3D processors are sometimes way more ahead than "just" 12%, some games scale a ton with X3D cache, so much that even 5800X3D wins against all Intel CPUs, so the "average 12%" doesn't mean that much, depending which games you play.

 

[john_]

It seems that not just software, like games, are prematurely release in beta states, but also hardware.

 

[Crackong]

Could Be

I 'll believe it when I see it, could be.

 

[piloponth]

It won’t help! That CPU is bad architectonally - the P-cores are separated by several hops over E-cores on the ring-bus!

If P-core (where main threads of the game shoud run) wants to talk to other P-core, there are at least 5 hops (4 E-cores, then P-core) which is a latency that any microcode update cannot overcome.

They simply messes the arch in chasse of better thermals by spreading P-cores around the sillicon. Better luck next time Intel.

 

[Bwaze]

But if I was to speculate, Intel wouldn't bother with such an update if it didn't at least bring "Arrow Lake" to the same degradation level as "Raptor Lake," if not higher!

 

[Wasteland]

It won’t help! That CPU is bad architectonally - the P-cores are separated by several hops over E-cores on the ring-bus!

If P-core (where main threads of the game shoud run) wants to talk to other P-core, there are at least 5 hops (4 E-cores, then P-core) which is a latency that any microcode update cannot overcome.

They simply messes the arch in chasse of better thermals by spreading P-cores around the sillicon. Better luck next time Intel.

The man's so polite, he writes his criticisms in invisible ink

 

[wolar]

It won’t help! That CPU is bad architectonally - the P-cores are separated by several hops over E-cores on the ring-bus!

If P-core (where main threads of the game shoud run) wants to talk to other P-core, there are at least 5 hops (4 E-cores, then P-core) which is a latency that any microcode update cannot overcome.

They simply messes the arch in chasse of better thermals by spreading P-cores around the sillicon. Better luck next time Intel.

Cant you disable E cores to not go through them then ?

 

[Scattergrunt]

A wunderwaffe won't save these CPUs.

Neither would a thunder-gun at this rate. Still though, for current owners of them this could be nice. But they already killed any momentum they had, so I doubt this will save them.

 

[usiname]

Cant you disable E cores to not go through them then ?

This won't change the physical distance between the cores

 

[phanbuey]

12% is good, some windows updates would be good too.

Still won't catch AMD but at least it will be a viable choice for all-rounder builds.

 

[Mitohondri]

It seems that not just software, like games, are prematurely release in beta states, but also hardware.

Yeah, its a trend in last 10 years in all areas.

Half assed products come on the market, and consumers are used as tester, then they are fixed on next gen releases, cars, motorbikes, mobile phones, notebooks, tv-s etc etc, and no one is held responsible.

Consumers just raise their concerns on various social media, and thats it. No lawsuits, no changes in the laws, no punishment for manufacturers, and we as idiots continue to buy defected products.

No one cares

 

[DemonicRyzen666]

It won’t help! That CPU is bad architectonally - the P-cores are separated by several hops over E-cores on the ring-bus!

If P-core (where main threads of the game shoud run) wants to talk to other P-core, there are at least 5 hops (4 E-cores, then P-core) which is a latency that any microcode update cannot overcome.

They simply messes the arch in chasse of better thermals by spreading P-cores around the sillicon. Better luck next time Intel.

Stopping at E-cores isn't 4 added stops, it's one because they all share a single slice of L3 cache to a cluster or 4 E-cores.

It is not P-core- to E-core to E-core to E-core to E-core to P-core.

It is P-core to E-core cluster to P-cores

 

[londiste]

There's still no word on the extent of gaming performance gain from this microcode, but if we were to speculate, Intel wouldn't bother with such an update if it didn't at least bring "Arrow Lake" to the same gaming performance level as "Raptor Lake," if not higher.

That is a very baseless speculation. Sure they would. Performance increases are a good thing in any case, no?

Same with the headline which is by all indications a baseless clickbait.

 

[mtosev]

It would be great if the microcode update would improve the performance.

 

[bug]

Stopping at E-cores isn't 4 added stops, it's one because they all share a single slice of L3 cache to a cluster or 4 E-cores.

It is not P-core- to E-core to E-core to E-core to E-core to P-core.

It is P-core to E-core cluster to P-cores

Not even that, because the middle 8 P-cores still sit next to each other.

Sure, the gaming performance is a little below previous gen. But considering how many (half)cores were lost in the transition, I say that's still a strong showing. I mean, if I were building for scratch and decided for Intel, I would build around Arrow Lake.

 

[redeye]

So they tune the microcode for benchmarks, fails.., tune it for gaming, GOLD, success, plaid Speed!…

 

[HD64G]

With Win11 24H2 official for a month now, the difference in performance between 9800X3D and 285K is more than 20% and not 12%. So, whatever improvement that firmware update brings to the table, the newest flagships are solar systems apart, at least in CPU sensitive game engines.

 

[rv8000]

12% is good, some windows updates would be good too.

Still won't catch AMD but at least it will be a viable choice for all-rounder builds.

The gap starts to become much larger the more games are tested it seems…

 

[Carlyle2020hs]

Me having to read the word "magic" in a tech article:

 

[Wolverine2349]

Stopping at E-cores isn't 4 added stops, it's one because they all share a single slice of L3 cache to a cluster or 4 E-cores.

It is not P-core- to E-core to E-core to E-core to E-core to P-core.

It is P-core to E-core cluster to P-cores

And that design sucks. Why bork what wasn't broke and worked so much better on Alder Lake and Raptor Lake where the P cores were together and e-cores on the side with still good latency even going to e-core though not as good and excellent. That way P cores were prioritized and e-cores the great secondary auxiliary threads kicked in when needed and it worked very well. And for stuff that scaled to infinite threads it did not matter.

Yes I know e-cores on Arrow Lake being Skymont are a lot stronger, but they still are not as strong as Intel claimed (LMAO Raptor Cove IPC lol, well maybe in cherry picked tests of IPC but not all rounder), so e-cores still not as good and cramming clusters in middle of p cores was a bad design choice.



And I do not think this update will help gaming that much. The tile based latency is real and its not gonna magically make it better or even on par with Raptor Lake which is a monolithic die that has a faster ring clock and P cores better in FP IPC and not far off in Integer IPC with as fast or faster clocks.