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Editorial Intel 18A Yields Are Actually Okay, And The Math Checks Out

AleksandarK

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A few days ago, we published a report about Intel's 18A yields being at an abysmal 10%. This sparked quite a lot of discussion among the tech community, as well as responses from industry analysts and Intel's now ex-CEO Pat Gelsinger. Today, we are diving into known information about Intel's 18A node and checking out what the yields of possible products could be, using tools such as Die Yield Calculator from SemiAnalysis. First, we know that the defect rate of the 18A node is 0.4 defects per cm². This information is from August, and up-to-date defect rates could be much lower, especially since semiconductor nodes tend to evolve even when they are production-ready. To measure yields, manufacturers use various yield models based on the information they have, like the aforementioned 0.4 defect density. Expressed in defects per square centimeter (def/cm²), it measures manufacturing process quality by quantifying the average number of defects present in each unit area of a semiconductor wafer.

Measuring yields is a complex task. Manufacturers design some smaller chips for mobile and some bigger chips for HPC tasks. Thus, these two would have different yields, as bigger chips require more silicon area and are more prone to defects. Smaller mobile chips occupy less silicon area, and defects occurring on the wafer often yield more usable chips than wasted silicon. Stating that a node only yields x% of usable chips is only one side of the story, as the size of the test production chip is not known. For example, NVIDIA's H100 die is measuring at 814 mm²—a size that is pushing modern manufacturing to its limits. The size of a modern photomask, the actual pattern mask used in printing the design of a chip to silicon wafer, is only 858 mm² (26x33 mm). Thus, that is the limit before exceeding the mask and needing a redesign. At that size, nodes are yielding much less usable chips than something like a 100 mm² mobile chip, where defects don't wreak havoc on the yield curve.




Next, the problem occurs with the actual design of a chip. Each silicon print for each specific chip will carry its signature pattern to be etched onto the silicon wafer. Each design carries its problems and defect rates, where specific placement of wires and transistors onto the silicon wafer can accumulate a lot more defects than other specific designs ready for manufacturing. Even when a chip is designed and ready, it still sometimes gets small redesigns to improve final yields. Remember that makers like NVIDIA pay TSMC the same regardless of its yields, so increasing the yields and improving the design is saving NVIDIA silicon that would otherwise go to waste or trickle down to non-flagship SKUs.

To calculate yields, manufacturers use various yield models—mathematical equations that help fabs better understand and predict yield loss by translating defect density distributions into yield predictions. While several models exist (including Murphy, Exponential, and Seeds models), the fundamental Poisson Yield Model (Y = e^(-AD)) assumes randomly distributed point defects, where Y is yield, A is chip area, and D is defect density. This model is derived from Poisson's probability distribution, which calculates the likelihood of zero defects occurring on a chip. However, the Poisson model is often considered pessimistic because real-world defects tend to cluster rather than distribute randomly, typically resulting in higher actual yields than the model predicts. Manufacturers choose their yield model by comparing various models' predictions against their actual fab data, selecting the one that best fits their specific manufacturing process and conditions.

When using the older data of the Intel 18A node, that d0=0.4, we must check a few different designs and compare their yields before drawing any conclusions. We are today measuring yields using the SemiAnalysis Die Yield Calculator tool, integrating all known yield models, Murphy, Exponential, Seeds, and Poisson. At the EUV reticle size limit of 858 mm² and with an applied 0.4 defect rate of 18A node, the most pessimistic estimate is the Poisson model, which gives a yield of 3.23%. However, the most optimistic (Seeds) model yields 22.56%. The default Murphy's model is yielding only 7.95% of usable chips. That is five good dies on a 300 mm wafer with 59 leftover dies.

A while back, we covered a leak of "Panther Lake," Intel's next-generation Core Ultra 300 series CPUs. The leaked package thankfully included information about die sizes, which we can input into the calculator to find out the yield, assuming Intel is manufacturing Panther Lake compute tiles on the 18A node, using the aforementioned d0 of 0.4. The die number four with a CPU and NPU on it, measuring 8.004x14.288 mm, a 114.304 mm² silicon die, gives a yield of 64.4% on the default Murphy's model. Moore's model is the most pessimistic, with only about 50% of usable dies. The die number five of Panther Lake, housing the Xe3 GPU, is even smaller and measures only 53.6 mm², yielding an impressive 81% of usable dies. Even with the most pessimistic assumptions, the yield curve drops to 60%.

If we assume that Intel has refined its 18A node more, we can conclude that even with some larger designs hitting the EUV machine reticle limit of 858 mm², Intel's yields could be hitting the 50% mark. If we assume that the best player TSMC achieves a 0.1 defect rate, yields of chips at 858 mm² size are barely above 50% using all available models. That is the fully functioning silicon die, of course. Non fully functional dies are later repurposed for lower-end SKUs. With modern Foveros and EMIB packaging, Intel could use smaller dies and interconnect them on a larger interposer to act as a single uniform chip, saving costs and boosting its yields. However, this is only a part of the silicon manufacturing story, as manufacturers use other techniques to save costs.

The initial reported Broadcom disappointment with Intel 18A node was prior to the PDK 1.0, which we assume is now in customer's hands to optimize their designs for version 1.0. Additionally, Intel should be enabling a few more optimizations based on the initial defect rate reported in August. Indeed, the revamp of Intel Foundry has been difficult, and the ousting of CEO Pat Gelsinger may have been a premature move. The semiconductor manufacturing supply chain takes years to fix; it isn't exactly a kid's toy manufacturing supply chain but rather the world's most advanced and complex industry. We assume that the Intel 18A node is fully functional and that we will see external customers pick up Intel's business significantly. Of course, in the beginning, Intel will be its own biggest customer until more fabless designers start rolling in.

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So make me an 18a nxxx chip with 2 memory channels that sips power but performs like a champ,already!
 

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I posted that something doesn't quite add up. And someone else pointed out the 10% was probably about Broadcom's humongous dies.
 

AleksandarK

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So all that to say that the original article you published with the 10% yield was at best misleading ?
The original article was a reporting on a report. Not our own made up story. Its our job to report on these news, and sometimes, like today, we do a little extra research to see what the real deal is. :)
 
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So all that to say that the original article you published with the 10% yield was at best misleading ?
It was a quote by some organisation quoting someone at Broadcom.
it gained a lot of traction like anything negative about intel in the tech press.

so its understandable tpu passed it trough the system too.
It is nice to see the counter, I doubt I’ll be reading that on sites like thg and others that don’t have editorial freedom
 

bug

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The original article was a reporting on a report. Not our own made up story. Its our job to report on these news, and sometimes, like today, we do a little extra research to see what the real deal is. :)
Sometimes? So due diligence is optional now, roger that.
 

bug

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there was much intel-mocking in that post's comment section, but also someone pointing out the unique considerations given broadcomm's requirements.
I think theres no fun to kick someone while they're down. and this effect stacks multiplicatively. Disclosure I own shares of INTC so holding the bag indeed
 
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I think Intel is just (trying) doing some heavy damage control for their shareholders.
It is visible from the Moon.
Dark side of the Moon...
 
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there was much intel-mocking in that post's comment section, but also someone pointing out the unique considerations given broadcomm's requirements.
I think theres no fun to kick someone while they're down. and this effect stacks multiplicatively. Disclosure I own shares of INTC so holding the bag indeed
We also look at the facts as investors and Intel’s real track record when it comes to chip fabbing has been wanting as of late. Delays of 14 and 10 nm allowed TSMC to get ahead. The renaming of the nodes seemed sketchy. The barely used 4 and 3 nm processes did not give much reassurance. And the icing on the cake, the cancelled 20A process gave us all pause for thought.

It would not be out of bounds to be wary especially after the CEO was fired. Also sites like TPU won’t address the conflict of interest that would arise should IFS make chips for competing companies. Since Intel said IFS was open for business in 2021, no major customers have jumped on board and no revenue from third parties has been reported. No CEO in their right mind of a competing company would have Intel make its products. This also limits Intel’s ability to optimize node processes for chips other than their own.
 
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We also look at the facts as investors and Intel’s real track record when it comes to chip fabbing has been wanting as of late. Delays of 14 and 10 nm allowed TSMC to get ahead. The renaming of the nodes seemed sketchy. The barely used 4 and 3 nm processes did not give much reassurance. And the icing on the cake, the cancelled 20A process gave us all pause for thought.

It would not be out of bounds to be wary especially after the CEO was fired. Also sites like TPU won’t address the conflict of interest that would arise should IFS make chips for competing companies. Since Intel said IFS was open for business in 2021, no major customers have jumped on board and no revenue from third parties has been reported. No CEO in their right mind of a competing company would have Intel make its products. This also limits Intel’s ability to optimize node processes for chips other than their own.
i did not feel like at any point that firing pat gelsinger was a good decision. time will tell but im not looking forward to it
 
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Until Intel can show they are back on track with process tech, they will get this heavy-to-unfair scrutiny. The proof is in the pudding, and Intel had to use someone else's box mix for Arrow Lake. I hope they do get it straightened out.
 
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By the time Intel actually produces chips on a new lithography they are going to need a 16A.
 
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Until Intel can show they are back on track with process tech, they will get this heavy-to-unfair scrutiny. The proof is in the pudding, and Intel had to use someone else's box mix for Arrow Lake. I hope they do get it straightened out.
Exactly. Why use Intel when Intel doesn’t even use Intel.
 
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By the time Intel actually produces chips on a new lithography they are going to need a 16A.
This is why Intel decided to try and effectively skip 20A. Probably pulling resources and bringing forward the cost of reconfiguration time. Current roadmap puts 18A volume production in second half of 2025 which is quite a bit away and based on what Intel themselves have stated so far should be a realistic target. They seem to be trying to speed this up and get production going faster but even their own confidence in getting it moving faster does not appear to be high.
 

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Until Intel can show they are back on track with process tech, they will get this heavy-to-unfair scrutiny. The proof is in the pudding, and Intel had to use someone else's box mix for Arrow Lake. I hope they do get it straightened out.
I'm with you. Even I have said they kinda ran out of credit with me, even though I don't like bashing companies.
The trouble is, it's not clear what "back on track" means. For the longest time, competitors used made up numbers to make it look like they were hot on Intel's heels. Now Intel has started playing that game, too. And roadmaps can change for 1,00o reasons beside the fab process. I, for one, cannot tell where the track is anymore.
 
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Intel 18A Yields Are Actually Okay, And The Math Checks Out

The headline is a statement, while the article contains not a few instances of words such as of "could", "assume", "probably", "estimate".
I would rather choose words for the headline more carefully: "Intel 18A yields could be actually okay, ..."
You may have the best technology in the world but it will be near to useless in wrong hands. One thing is technology, the other is how to operate.
These models that are used to calculate die yields might not take into account that fact.

If yields are really okay, why has Intel not published any related news yet? Intel was so excited about 18A being able to boot so they released a whole new press article.
Basically, if you're dealing with the shitstorm that Intel currently is, you'd publish ANY good news as damage control. Why no good news, only speculations?
Intel 18A may not be a bad process, but most probably suited for (smaller) chiplets only. Not for Nvidia and Broadcom.

there was much intel-mocking in that post's comment section, but also someone pointing out the unique considerations given broadcomm's requirements.
I think theres no fun to kick someone while they're down. and this effect stacks multiplicatively. Disclosure I own shares of INTC so holding the bag indeed
And making unrealistic statements, not disclosing problems about oxidation and burning issues, as well as lying to customers/shareholders was also not fun, right?
They are down because of their own doing, because of their own marketing bullshit. If you make customers to expect big things, they get easily disappointed should you fail to deliver.
 
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If yields are really okay, why has Intel not published any related news yet? Intel was so excited about 18A being able to boot so they released a whole new press article.
Basically, if you're dealing with the shitstorm that Intel currently is, you'd publish ANY good news as damage control. Why no good news, only speculations?
Intel 18A may not be a bad process, but most probably suited for (smaller) chiplets only. Not for Nvidia and Broadcom.
There are no interesting steps between booting some chips and getting something mass produced. Some form of gradually reducing defect density and that is about it. 18A should be somewhere on the verge of mass production and this is most likely the next news Intel will publish - mass producing this-or-that. After making sure yields are reasonably OK of course.

Also, news was not about 18A booting. They had test stuff that was working earlier. August news was about booting Panther Lake and Clearwater Forest dies produced on 18A.
They also stated that first external customer tape-out is 2025H1 which should give us a timeframe.
 
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good stuff, except it will be expensive. (ps5pro expensive, meaning nobody but hardcore people buy it )

yet, how is TSMC’s similar process coming along… better? Compared to intel…
 
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The original article was a reporting on a report. Not our own made up story. Its our job to report on these news, and sometimes, like today, we do a little extra research to see what the real deal is. :)
Well since you’re clearly capable of doing research, why didn’t you do the research before publication?

It took being called out as “fake news” by many on twitter (including Pat Gelsinger) for you to add the necessary context.
 
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Intel said they have defect density 0.4, but it is unknown if this is average density on minimal on best part of wafer. So total PTL yield from wafer may be lower.
 

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Good news, lets make some calculators boys :rockout:
 
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