Editorial Intel 18A Yields Are Actually Okay, And The Math Checks Out

[Daven]

Well since you’re clearly capable of doing research, why didn’t you do the research before publication?

It took being called out as “fake news” by many on twitter (including Pat Gelsinger) for you to add the necessary context.

Should Intel be held to the same standards and not allowed to release any powerpoint slides about products unless they have been released and available to the public? How many times has a code name or process technology never seen the light of day at Intel?

By my count, Intel has lied so many times and cancelled so many products that never were; all just to keep the stock price from tanking that their proverbial nose could reach orbit. How are news sites suppose to publish 100% accurate info under such conditions?

TPU is doing just fine and I always wear my big boy pants when I go onto the internet looking for information. I can figure out things for myself.

 

[Nanochip]

Should Intel be held to the same standards and not allowed to release any powerpoint slides about products unless they have been released and available to the public? How many times has a code name or process technology never seen the light of day at Intel?

By my count, Intel has lied so many times and cancelled so many products that never were; all just to keep the stock price from tanking that their proverbial nose could reach orbit. How are news sites suppose to publish 100% accurate info under such conditions?

TPU is doing just fine and I always wear my big boy pants when I go onto the internet looking for information. I can figure out things for myself.

Some of us didn’t know how defect density translates into yield percentages… or that chip size is a very relevant consideration. Context is always helpful, especially when rebroadcasting rumors that are potentially harmful to a company’s reputation or stock price. You don’t want to unwittingly be a vector of fake news yourself.

 

[Visible Noise]

Intel said they have defect density 0.4, but it is unknown if this is average density on minimal on best part of wafer. So total PTL yield from wafer may be lower.

It was also four months ago. Who thinks yields havn’t improved?

 

[damric]

RAJA KOUDRI for INTEL CEO

 

[Darmok N Jalad]

Really, the process nose itself only matters in the advantage it brings. Arrow Lake is on a pretty new process, but it’s not winning them benchmarks, but it does offer some efficiency gains. Intel’s 14nm+++ was pretty old, but it was proven, and it was sufficient to give Intel a performance advantage, at the cost of efficiency. I don’t know that Intel necessarily needs to have the best node, but the best design for the node they are using. Hasn’t NVIDIA been basically doing just that?

 

[Post Nut Clairvoyance]

Someone in general - not fun.
Intel - extremely fun!

I meant the amount of half hate (which is deserved all things considered) half mocking posts, which is a lot of bitterness.
I am not at all opposed to mocking intel. And that post was old technology, intel has had much meme materials since then (anyone watching gn would have couple ideas)

 

[scottslayer]

So is this the unofficial "correction" post after getting dunked on by literally everyone and their mother in the tech sector?

 

[Chaitanya]

This same Pat Gelsinger is calling out yeild rates?

Fired Intel CEO: Will fast this week for 100,000 Intel employees as they … - The Times of India

TECH NEWS : Ousted Intel CEO Pat Gelsinger has called for prayers and fasting for the company's employees amid a turbulent period. Following a significant stock d

timesofindia.indiatimes.com

 

[Robin Seina]

I think, the author of the article should check-out this one link below, since it looks like he forgets that yield is not just defect rate.

Výtěžnost v procentech nebo denzita defektů? Rozhodně nejde o totéž. | Diit.cz

diit-cz.translate.goog

 

[londiste]

I think, the author of the article should check-out this one link below, since it looks like he forgets that yield is not just defect rate.

Výtěžnost v procentech nebo denzita defektů? Rozhodně nejde o totéž. | Diit.cz

diit-cz.translate.goog

The link brings nothing new to the discussion.

Clock speeds, leak voltages and other parameters are usually handled and phrased separately from yield. The 10% yield number matches very well with defect rate Intel has publicly stated, if the die size is very large. Broadcom does have enormous dies for the chips like the one the news bit said was being evaluated. Lacking other details this is the easiest conclusion to come to.

Lunar Lake - same as Arrow Lake - came now, at a time when by Intel's own claim 18A is just starting to become ready. Given the delays from starting production to launching a product, neither 20A nor 18A were simply not possible for either of those. The questions for Lunar Lake and Arrow Lake might be what is going on with Intel 3 but that one most likely has a very simple answer - Xeons.

 

[Robin Seina]

Lunar Lake - same as Arrow Lake - came now, at a time when by Intel's own claim 18A is just starting to become ready. Given the delays from starting production to launching a product, neither 20A nor 18A were simply not possible for either of those. The questions for Lunar Lake and Arrow Lake might be what is going on with Intel 3 but that one most likely has a very simple answer - Xeons.

If 18A is at great condition and becoming ready, why is Intel reserving production space at TSMC' 3nm and 2nm processes for its CPU production?

 

[Hecate91]

The defect rate could be anything between what Broadcom claims and what others claim, even though it seems like damage control.
But if the yields were fine Intel would be using 18A instead of TSMC for Arrow Lake.

 

[londiste]

If 18A is at great condition and becoming ready, why is Intel reserving production space at TSMC' 3nm and 2nm processes for its CPU production?

This isn't black and white. Intel is reserving production on TSMC. For what exactly we are not sure. They will be producing GPUs at TSMC, AI and other data center stuff as well. Last desktop CPUs with tiles will need SoC and iGPU dies and Intel is primarily focused on producing the compute dies on their own - if they can.

Remember that in August alongside news they did show Panther Lake with at least compute die supposedly produced on 18A. If I remember correctly Panther Lake is on roadmap for 2025H2. Production is only starting and it is quite a few quarters to go before we see a launched product.

 

[LittleBro]

There are no interesting steps between booting some chips and getting something mass produced. Some form of gradually reducing defect density and that is about it. 18A should be somewhere on the verge of mass production and this is most likely the next news Intel will publish - mass producing this-or-that. After making sure yields are reasonably OK of course.

Also, news was not about 18A booting. They had test stuff that was working earlier. August news was about booting Panther Lake and Clearwater Forest dies produced on 18A.
They also stated that first external customer tape-out is 2025H1 which should give us a timeframe.

So news about something being stable enough just to boot is much more important/interesting than news about process itself?
Stakeholders don't give a **** about booting. They don't even know what word "to boot" stands for.
All they want to know is information on their investments, meaning how many chips can be produced at what cost and what will they sell for.
Everything is about money, after all. Delivering on technology is not the end goal. The end goal is being financially successful.

With such pile of shit Intel is dealing right now, I think their press release dept. would release anything just to mitigate this desperate situation.
Huge layoffs and firing Gelsinger in middle of process in nothing else but a proof to the fact that Intel is encountering serious troubles right now.

There's a saying: A drowning man will clutch at a straw.

 

[londiste]

Looks like I was wrong, there are news to be made from interim steps

Intel "Panther Lake" Confirmed on 18A Node, Powering-On With ES0 Silicon Revision

During Barclays 22nd Annual Global Technology Conference, Intel was a guest and two of the interim company co-CEOs Michelle Johnston Holthaus and David Zinsner gave a little update on the state of affairs at Intel. One of the most interesting aspects of the talk was Intel's upcoming "Panther...

www.techpowerup.com

 

[LittleBro]

Looks like I was wrong, there are news to be made from interim steps

Intel "Panther Lake" Confirmed on 18A Node, Powering-On With ES0 Silicon Revision

During Barclays 22nd Annual Global Technology Conference, Intel was a guest and two of the interim company co-CEOs Michelle Johnston Holthaus and David Zinsner gave a little update on the state of affairs at Intel. One of the most interesting aspects of the talk was Intel's upcoming "Panther...

www.techpowerup.com

So finally, after booting up, it powers on!

... said interim co-CEO Michelle Johnston Holthaus, adding, "But just to give some assurances, on Panther Lake, we have our ES0 samples out with customers. We have eight customers that have powered on, which gives you just kind of an idea that the health of the silicon is good and the health of the Foundry is good." - Intel

So if I power a chip on, that means the silicon is good and health of the foundry that made that chip is good as well. Oh boy, I miss Pat already, he at least understood technology.
I just realized my 5600X is a godlike product! It not only powers on, then boots OS, but also does everything else and is stable.

So health of the foundry is good. What does it mean for foundry yield? What is considered good?
If you have been manufacturing 10% for a year, even moving to 20% yield might be considered good.

This is what you get when MBA graduate get's to assure customers about technology success.