PCI-SIG Releases PCI-Express Gen 7 Draft Specification 0.7—128 Gbps per Lane

[btarunr]

PCI-SIG, the consortium that governs the PCI Express I/O interconnect, released draft specification version 0.7 for the upcoming PCI-Express 7.0 standard (or PCIe Gen 7). An early-2025 release of this draft could indicate that PCIe Gen 7 gets finalized into specification version 1.0 by the end of 2025, from where implementers can pick it up to design their devices around. We are now at 32 Gbps per lane per direction with PCIe Gen 5, and PCIe Gen 6 doubles it to 64 Gbps, which would mean PCIe Gen 7 will double that further to 128 Gbps per lane per direction. PCI-Express 7.0 x1 would offer the same bandwidth as PCI-Express 3.0 x16. We could realistically expect the first computing platforms implementing PCIe Gen 7 to come out around 2027 or even 2028. PCIe forms the physical layer for a number of derivative standards, such as CXL, Thunderbolt, USB (USB 3.0 onwards), NVMe, SDexpress, CFexpress, and DMI.



Many Thanks to Tumble George for the tip

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[Oberon]

I'm just here for the DFI mobo.

 

[Chaitanya]

I'm just here for the DFI mobo.

Would really love to see DFI Lanparty making a comeback.

 

[Daven]

PCIe 1.0 2.5 GT/s
PCIe 2.0 5.0 GT/s
PCIe 3.0 8.0 GT/s
PCIe 4.0 16 GT/s
PCIe 5.0 32 GT/s
PCIe 6.0 64 GT/s
.
.
and now...
PCIe 7.0 128 GT/s...I did not see that coming.

What would we do without these standards organizations.

 

[fynxer]

PCIe 1.0 2.5 GT/s
PCIe 2.0 5.0 GT/s
PCIe 3.0 8.0 GT/s
PCIe 4.0 16 GT/s
PCIe 5.0 32 GT/s
PCIe 6.0 64 GT/s
.
.
and now...
PCIe 7.0 128 GT/s...I did not see that coming.

What would we do without these standards organizations.

Concur, predictable and sad.

We can never get enuf bandwidth, specially now with AI, so why not push the limits of PCIe 7.0 to192 GT/s or even 256GT/s.

It takes several years to evolve just one step forward in a standard like PCIe, better go for the maximum performance each time.

Why double if you can triple or even quadruple each evolution of a standard, if it can be done they should do it.

These incremental upgrades of different standards set in a predefined pattern is a decease in many industries holding back progress and delaying human evolution by years or even decades.

Capitalism at it's best, hold back progress as much as possible to make as much money as long as possible with small and predictable upgrades, NVIDIA done it for years.

There is a reason NVIDIA accelerated it's development of new generations from every two years to every year.

Competition from ASIC is pressuring NVIDIA to expand with 1000 new engineers to push development to the maximum immediately or they will become obsolete in the AI arena in the near future.

ASICs vs. GPUs: Is Nvidia's AI Dominance at Risk?

 

[Daven]

Concur, predictable and sad.

We can never get enuf bandwidth, specially now with AI, so why not push the limits of PCIe 7.0 to192 GT/s or even 256GT/s.

It takes several years to evolve just one step forward in a standard like PCIe, better go for the maximum performance each time.

Why double if you can triple or even quadruple each evolution of a standard, if it can be done they should do it.

These incremental upgrades of different standards set in a predefined pattern is a decease in many industries holding back progress and delaying evolution by years or even decades.

Seeing as the trend started at 2.5 then 5 GT/s and then slowed to 8 GT/s, I don't see that happening. If the original trend had held, at least 160 GT/s would be the value under 7.0.

 

[Tomorrow]

So 2030 and beyond. Not before. Assuming we get 6.0 in 2027 or so.

 

[FoxFireMK]

That is a DFI LanParty nF4 in the picture. One of the first PCIe mainboards.

 

[Solid State Brain]

It'll be amazing when GPU-RAM-CPU speeds won't be so constrained anymore by PCIe limitations. With upcoming DDR6 memory, under multi-channel configurations, bandwidth should get fast enough that VRAM-less GPUs may even be possible.

 

[nageme]

and now... PCIe 7.0 128 GT/s...I did not see that coming.
What would we do without these standards organizations.

The standard isn't the numeric speed, but the technology to achieve that speed.

 

[Nhonho]

PCIe 1.0 2.5 GT/s
PCIe 2.0 5.0 GT/s
PCIe 3.0 8.0 GT/s
PCIe 4.0 16 GT/s
PCIe 5.0 32 GT/s
PCIe 6.0 64 GT/s
.
.
and now...
PCIe 7.0 128 GT/s...I did not see that coming.

What would we do without these standards organizations.

PCIe Gen 5

Can the TPU staff please do tests with RTX 5000 cards to we see the impact of using a VGA PCIe 5.0 on previous generation PCIe slots?

 

[nageme]

@Nhonho

A summary table on Wikipedia is somewhat different:

 

[ymdhis]

Hopefully by then, videocards with m.2 slots via bifurcation will be the standard, can't see how a consumer card would need 128 x 16 GT/s, half or even quarter of that will be enough, and we can use the rest for more NVME storage. With m.2 slots on the videocard, it will also be very space efficient for small form factor builds.

PCIe 1.0 2.5 GT/s
PCIe 2.0 5.0 GT/s
PCIe 3.0 8.0 GT/s
PCIe 4.0 16 GT/s
PCIe 5.0 32 GT/s
PCIe 6.0 64 GT/s
.
.
and now...
PCIe 7.0 128 GT/s...I did not see that coming.

What would we do without these standards organizations.

The interesting part isn't the doubling of speed, it's what technology and data encoding they use to reach that speed on the same physical connector.

 

[persondb]

Seeing as the trend started at 2.5 then 5 GT/s and then slowed to 8 GT/s, I don't see that happening. If the original trend had held, at least 160 GT/s would be the value under 7.0.

From PCIe 2 to 3 there was a change in the encoding, that mostly made up for the 5 GT/s to 8 GT/s, so it still was roughly a doubling.
PCIe Gen 2 and earlier use 8b/10b, so it means that 5 GT/s is actually 4 GT/s after you remove the encoding overhead.

 

[Nhonho]

@Nhonho

A summary table on Wikipedia is somewhat different:

Yes, for commercial purposes, it was published that PCIe 3.0 has a throughput of 1 GB/s per lane, but in fact, the real values are those in this Wikipedia table.

data encoding they use to reach that speed on the same physical connector.

It was necessary to achieve the speed of PCIe 3.0 and later. The encoding of PCIe 1 and 2 was 10b/8b, which generated 20% overhead. And in computing, it is curious that, the larger the size of the data packet, the lower the % of overhead data required (only 1.5% of overhead data in the case of PCIe 3, 4 and 5).

A summary table on Wikipedia is somewhat different:

If we are being really strict, even the Wikipedia table is wrong, because each PCIe lane transfers data in both directions independently. So, for example, a PCIe 1.0 lane actually transfers 500 MB/s (250 MB/s in each direction).

 

[bonehead123]

Capitalism at it's best, hold back progress as much as possible to make as much money as long as possible with small and predictable upgrades, NVIDIA done it for years.

^^THIS^^

but you should add Intel and almost every other tech company onto the list....as they ALL are or have been guilty of this at one time or another !

 

[NoLoihi]

Hey, guys, have you considered that it’s technically hard to increase speeds? Doublings are huge increases. You’re sure it’s moving on its own and companies are just there to hold the brakes!?
*(Exponential, by the way. Same as we’ve got for CPU speeds, just at a vastly higher rate from one generation to the next.**)
**(Homework task: Find out where we stand, cumulating those gains, with CPU and GPU vs. PCIe speed, also in terms of storage. I’d love to see that spread out.)


Maybe, with more capital investment, movement could have been sped up even more … … … May you please remind me what the general opinion on faster PCIe standards was, please? Did you note any … issue with them? IDK, in terms of—well, not color fidelity, of course—maybe, rather: Temperatures, power draw, design constraints!? Did it get harder to design PCIe risers, for one? What do we know about trace lengths? Is there an increase in capital expenditure for every unit of product sold using those higher rates?

Yeah.