- Joined
- Aug 19, 2017
- Messages
- 2,758 (1.01/day)
AMD's upcoming Instinct MI400 accelerator series, scheduled for 2026 introduction, is set to incorporate a new Multimedia IO Die (MID) architecture alongside significant compute density improvements. According to recent patches discovered in AMD-GFX mailing lists, the accelerator will feature a dual Active Interposer Die (AID) design, with each AID housing four Accelerated Compute Dies (XCDs)—doubling the XCD count per AID compared to the current MI300 series. Introducing dedicated Multimedia IO Dies is a new entry in AMD's accelerator design philosophy. Documentation reveals support for up to two MIDs, with each likely paired to an AID, suggesting a more specialized approach to multimedia processing and interface management.
Specifications from the Register Remapping Table (RRMT) implementation indicate sophisticated die-to-die communication pathways, with support for local and remote transactions across XCDs, AIDs, and the new MIDs. The system enables granular control over eight potential XCD configurations (XCD0 through XCD7), suggesting that AMD can scale compute up and down with SKUs. While AMD has yet to release detailed specifications for the MI400 series, separating multimedia functions into dedicated dies could optimize performance and power efficiency. As the 2026 launch window approaches, AMD will spend the remaining time refining the software stack and ROCm support for its next-generation accelerator based on UDNA architecture. Since designing an accelerator is a year-long effort from the physical implementation standpoint, we expect the Instinct MI400 design to be finalized by now. All left is silicon bring-up, software optimization, and mass production, likely at TSMC's facilities.
View at TechPowerUp Main Site | Source
Specifications from the Register Remapping Table (RRMT) implementation indicate sophisticated die-to-die communication pathways, with support for local and remote transactions across XCDs, AIDs, and the new MIDs. The system enables granular control over eight potential XCD configurations (XCD0 through XCD7), suggesting that AMD can scale compute up and down with SKUs. While AMD has yet to release detailed specifications for the MI400 series, separating multimedia functions into dedicated dies could optimize performance and power efficiency. As the 2026 launch window approaches, AMD will spend the remaining time refining the software stack and ROCm support for its next-generation accelerator based on UDNA architecture. Since designing an accelerator is a year-long effort from the physical implementation standpoint, we expect the Instinct MI400 design to be finalized by now. All left is silicon bring-up, software optimization, and mass production, likely at TSMC's facilities.
View at TechPowerUp Main Site | Source
