- Joined
- Aug 19, 2017
- Messages
- 2,774 (1.02/day)
Intel's upcoming "Nova Lake" desktop processors are taking shape slowly, featuring a three-tier core design that could reach 52 total cores. Set for 2026, the flagship SKU combines 16 "Coyote Cove" P-cores with 32 "Arctic Wolf" E-cores, supplemented by 4 LPE-cores for background task management. Intel is reportedly also considering 28-core (8P + 16E + 4LPE), and 16-core (4P + 8E + 4LPE) SKUs too. The architectural design choice centers on Intel's hybrid manufacturing approach, leveraging both its internal 14A node and TSMC's 2 nm process technology. This strategic decision addresses supply chain resilience while potentially enabling higher yields for critical compute tiles. Intel's interim co-CEO Michelle Johnston Holthaus noted that Intel Foundry will need to earn Intel Product's trust with each new node, so if a node is not the best for their in-house IP, Intel will move to TSMC for production.
Initial engineering samples are already circulating among developers, according to shipping documentation from NBD, suggesting the validation phase is proceeding on schedule. Some specifications point to significant cache improvements, with documentation suggesting a 144 MB L3 cache implementation. However, the cache topology—whether unified or segmented—remains unspecified. The platform is expected to support PCIe Gen 6.0, though Intel has yet to confirm socket compatibility or memory specifications. However, we need to hold our expectations low. Previously unrealized configurations in Intel's roadmaps, like 40-core "Arrow Lake," never materialized, and instead, we got an eight-P-core version with 16 E-cores, totaling 24 cores. Final specifications may evolve as the platform progresses through development phases.
View at TechPowerUp Main Site | Source
Initial engineering samples are already circulating among developers, according to shipping documentation from NBD, suggesting the validation phase is proceeding on schedule. Some specifications point to significant cache improvements, with documentation suggesting a 144 MB L3 cache implementation. However, the cache topology—whether unified or segmented—remains unspecified. The platform is expected to support PCIe Gen 6.0, though Intel has yet to confirm socket compatibility or memory specifications. However, we need to hold our expectations low. Previously unrealized configurations in Intel's roadmaps, like 40-core "Arrow Lake," never materialized, and instead, we got an eight-P-core version with 16 E-cores, totaling 24 cores. Final specifications may evolve as the platform progresses through development phases.
![](https://www.techpowerup.com/img/EDKP29yZZuQRiGsj_thm.jpg)
View at TechPowerUp Main Site | Source