Sin
News Editor
- Joined
- Mar 28, 2011
- Messages
- 244 (0.05/day)
- Location
- under the bed
Toshiba Corporation today announced that the development of the world's first MROM cell to offer improved cell current characteristics without any increase in cell size. This advance was achieved by adopting a multi-level-cell structure, which also secures high speed operation. Details will be presented on June 14 at the 2013 Symposia on VLSI Technology and Circuits, held in Kyoto, Japan, June 11-14, 2013.
MROM's main role is to store the boot loader or firmware. The density of MROM implemented is SoC for such digital applications as smartphones and tablet PCs is increasing year by year, and in order to improve access time it is necessary to halve the MROM cell area with every generation.
In a typical MROM bit cell, a single-level cell, variations in fabrication are increasing as SoC process technology advances, with the narrowing of the channel area of the cell transistors. The result is a slower access time for the 40nm generation than for the previous process generation. Improving access time requires a larger transistor, as a bigger cell area secures a wider channel area.
Toshiba has developed a multi-bit cell that uses twice the area of a standard single level cell, successfully expanding channel width in the cell transistor by three times. This also triples the current characteristic of the cell without any change in the memory capacity per area. It reduces the influence of the variation in fabrication by 42%.
Toshiba has developed of MROM cell with the 40nm process generation and aims to ship SoC for digital applications that implement the cell in 2014.
View at TechPowerUp Main Site
MROM's main role is to store the boot loader or firmware. The density of MROM implemented is SoC for such digital applications as smartphones and tablet PCs is increasing year by year, and in order to improve access time it is necessary to halve the MROM cell area with every generation.
In a typical MROM bit cell, a single-level cell, variations in fabrication are increasing as SoC process technology advances, with the narrowing of the channel area of the cell transistors. The result is a slower access time for the 40nm generation than for the previous process generation. Improving access time requires a larger transistor, as a bigger cell area secures a wider channel area.
Toshiba has developed a multi-bit cell that uses twice the area of a standard single level cell, successfully expanding channel width in the cell transistor by three times. This also triples the current characteristic of the cell without any change in the memory capacity per area. It reduces the influence of the variation in fabrication by 42%.
Toshiba has developed of MROM cell with the 40nm process generation and aims to ship SoC for digital applications that implement the cell in 2014.
View at TechPowerUp Main Site
