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Micron Technology, Inc., one of the world's leading providers of advanced semiconductor solutions, today announced its collaboration with Broadcom Corporation to develop the industry's first solution designed for customers challenged by an intrinsic DDR3 timing parameter called tFAW, or four activate window.
tFAW refers to a DDR3 timing parameter that restricts data throughput in server, storage and networking applications and can compromise bandwidth by 15 to 35 percent. With every new DRAM generation, the access granularity is becoming double, causing some timing parameters like tRDD and tFAW to restrict data throughput. This creates challenges for high-performance applications because no more than four bank activate commands can be issued in any given tFAW period.
"The search for improved performance among network providers remains a challenge in the midst of continuous data overload," said Mike Howard, senior principal analyst of DRAM and memory at IHS iSuppli. "Architecture solutions that can open up bandwidth for high-performance applications will serve to extend operational efficiencies and boost overall network performance."
According to the Cisco Visual Networking Index, global IP traffic is projected to grow at a compound annual growth rate (CAGR) of 23 percent from 2012 to 2017.
To satisfy this overwhelming appetite for bandwidth, service providers around the globe are racing to transform their networks by adopting higher-bandwidth links.
The Micron solution validated by Broadcom reduces the tFAW value from 35ns to 30ns for a 2KB page size, DDR3-2133, improving operations per second by 18 percent. This performance increase is especially critical for complex packet processing functions, such as highly scalable IPv4 and IPv6 lookups used in service provider networking applications. The four activate window solution enables Broadcom's BCM88030 200 Gb/s NPU to achieve extremely scalable L2, IPv4 and IPv6 lookup capacities at wire speed performance using Micron's DDR3 memory.
"OEMs today continue to tackle the challenge of an ever-increasing volume, velocity and variety of data," said Robert Feurle, vice president of DRAM marketing at Micron. "We are delighted to be working with Broadcom to validate a solution that helps alleviate the throughput challenge for our mutual customers."
"Broadcom is committed to delivering the high-bandwidth capacity and scale to meet the aggressive requirements of next-generation networks," said Dan Harding, senior director of product marketing, compute & connectivity, Broadcom. "Through our collaboration with Micron, we continue our efforts to provide the most scalable NPU solutions in the industry."
Availability
Micron's 2Gb and 4Gb DDR3 with the reduced tFAW timing specification are available in volume production now.
Micron, a committed partner to the networking market, has a legacy of customer and partner collaboration, providing memory solutions and systems that accelerate the networking infrastructure connecting our world. For more information, visit micron.com.
View at TechPowerUp Main Site
tFAW refers to a DDR3 timing parameter that restricts data throughput in server, storage and networking applications and can compromise bandwidth by 15 to 35 percent. With every new DRAM generation, the access granularity is becoming double, causing some timing parameters like tRDD and tFAW to restrict data throughput. This creates challenges for high-performance applications because no more than four bank activate commands can be issued in any given tFAW period.
"The search for improved performance among network providers remains a challenge in the midst of continuous data overload," said Mike Howard, senior principal analyst of DRAM and memory at IHS iSuppli. "Architecture solutions that can open up bandwidth for high-performance applications will serve to extend operational efficiencies and boost overall network performance."
According to the Cisco Visual Networking Index, global IP traffic is projected to grow at a compound annual growth rate (CAGR) of 23 percent from 2012 to 2017.
To satisfy this overwhelming appetite for bandwidth, service providers around the globe are racing to transform their networks by adopting higher-bandwidth links.
The Micron solution validated by Broadcom reduces the tFAW value from 35ns to 30ns for a 2KB page size, DDR3-2133, improving operations per second by 18 percent. This performance increase is especially critical for complex packet processing functions, such as highly scalable IPv4 and IPv6 lookups used in service provider networking applications. The four activate window solution enables Broadcom's BCM88030 200 Gb/s NPU to achieve extremely scalable L2, IPv4 and IPv6 lookup capacities at wire speed performance using Micron's DDR3 memory.
"OEMs today continue to tackle the challenge of an ever-increasing volume, velocity and variety of data," said Robert Feurle, vice president of DRAM marketing at Micron. "We are delighted to be working with Broadcom to validate a solution that helps alleviate the throughput challenge for our mutual customers."
"Broadcom is committed to delivering the high-bandwidth capacity and scale to meet the aggressive requirements of next-generation networks," said Dan Harding, senior director of product marketing, compute & connectivity, Broadcom. "Through our collaboration with Micron, we continue our efforts to provide the most scalable NPU solutions in the industry."
Availability
Micron's 2Gb and 4Gb DDR3 with the reduced tFAW timing specification are available in volume production now.
Micron, a committed partner to the networking market, has a legacy of customer and partner collaboration, providing memory solutions and systems that accelerate the networking infrastructure connecting our world. For more information, visit micron.com.
View at TechPowerUp Main Site
